Interrupt Priority Registers A And B (Ipra, Iprb) - Hitachi H8/3062 Hardware Manual

SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
SSBY
Initial value
Read/Write R/W
Software standby
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as interrupt mask bit
1 UI bit in CCR is used as user bit
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG Description
0 Interrupt is requested at falling edge of NMI input
1 Interrupt is requested at rising edge of NMI input
5.2.2

Interrupt Priority Registers A and B (IPRA, IPRB)

IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
98
7 6
STS2 STS1
0 0
R/W R/W
Standby timer
select 2 to 0
5 4
STS0 UE
0 0
R/W R/W
User bit enable
Selects whether to use the UI bit in
CCR as a user bit or interrupt mask bit
3 2
NMIEG SSOE
1 0
R/W R/W
Software standby
output port enable
NMI edge select
Selects the NMI input edge
1 0
RAME
0 1
R/W
RAM enable
(Initial value)
(Initial value)