Reset; Clock Connection; Mcu Clock; Cc Clock - Fujitsu MB88121 Application Note

Interfacing MB91460 TO MB88121
Chapter 2 Hardware

2.2 Reset

The MCU (MB91F467D) and FlexRay CC (MB88121) support the Reset functionality via
external pin. Depending on Application both reset pin might be connected to an external
voltage supervisor chip, which controls the reset line or the MCU controls the reset pin of the
MB88121 via IO port. The example in this Application Note is using first mentioned
approach.
As MB88121 series is a single voltage supply series, care have to be taken in case the
MB91F467D series is using different voltage supply level at bus interface pins (Vdd35) and
other IO pins (Vdd). In this case ensure e.g. via level converter correct High level for
MB88121 series reset input pin.

2.3 Clock connection

Both devices require an external clock to generate the internal clock.

2.3.1 MCU Clock

For MB91460 series a 4 MHz external clock needs to be connected to X0 / X1 pins.
Via the internal PLL a clock of up to 10MHz is generated.

2.3.2 CC Clock

The MB88121 is requiring an internal clock of 80 MHz. This frequency is generated using a
PLL, supporting external clocks at pin X0 and X1.
4MHz, 5MHz, 8MHz or 10MHz crystal are supported.

2.4 Operation Mode of MCU and CC

Both devices need to be set to correct mode via mode pins.

2.4.1 MCU operation mode

The MD[2:0] pins of the MCU defines whether the reset vector is fetched from internal or
external area. In case the internal Flash memory shall be used the mode pins have to be set
to internal mode vector setting. During start-up phase of the MCU the bus interface settings
is configured via the bus interface registers.
The mode pins of MB91F467D should connect to GND directly so that the MCU operates in
the internal ROM external bus mode. The configuration of this mode is listed below.
Configuration Description
Mode pin
Internal mode vector and reset vector
MD[2:0]=0
Table 2-3 Configuration of internal ROM external bus mode
The memory map of this operation mode is illustrated in the next page. The gray memory
area is not available. By default settings in file Start91460.asm chip select areas are set as
non-cacheable areas (register ICHCR). For the Flash memory 8KB pre-fetch buffer is
enabled (register FCHCR). For details about Flash memory and its instruction cache, please
refer to the chapter 11 'Memory Controller' of MB91460 hardware Manual. Instruction cache
of external bus interface is declared in the chapter 12 'Instruction cache'.
MCU-AN-300016-E-V10 - 8 - © Fujitsu Microelectronics Europe GmbH