Reset - Fujitsu MB90895 Series Hardware Manual

CHAPTER 3 CPU
3.6

Reset

When a reset trigger even occurs, the CPU immediately suspends the current process
and starts the reset operation. The reset factors are as follows:
• Power on reset
• Watchdog timer overflow
• Generation of software reset request
• Generation of external reset request (RST pin)
I Reset Factor
Table 3.6-1 Reset Factor
Reset
Power on reset
Watchdog timer
reset
Software reset
External reset
MCLK: Main clock
G
Power on reset
• The power on reset occurs at power on.
• The reset operation is executed after the oscillation stabilization wait time of 2
G
Watchdog timer reset
• Unless the watchdog timer is periodically cleared at the interval time to be repeatedly counted after
starting, an overflow occurs, causing a reset.
• The oscillation stabilization wait time is not generated by a watchdog timer reset.
Note: For details on the watchdog timer, see CHAPTER 6 WATCHDOG TIMER.
G
Software reset
• The software reset occurs when "0" is written to the internal reset signal generation bit (LPMCR: RST)
in the low-power consumption mode control register.
• The oscillation stabilization wait time is not generated by a software reset.
G
External reset
• The external reset occurs when a Low level is input to the external reset pin (RST pin). The time for
96
Factor
At power on
Watchdog timer overflow
"0" is written to the RST bit
Input "L" level to RST pin
Machine Watchdog timer
clock
MCLK Stops
MCLK Stops
MCLK Stops
MCLK Stops
Oscillation Stabilization
Waiting
Yes
None
None
None
18
/HCLK has elapsed.