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CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
3.9
Reset Sequence
This section describes the reset operation for placing the CPU in operation status.
I Reset sources
The causes for reset are as follows:
•
Input from an external reset pin
•
Software reset by the SRST bit operation of the standby control register (STCR)
•
Count-up of the watchdog timer
•
Power-on reset
I Initialization by reset
If a reset source occurs, the CPU is initialized.
❍ Releasing the reset source from an external reset pin or software reset
•
Set the pin to the specified status.
•
Set each resource in the device to reset status. The control register is initialized to the
predetermined value.
•
The slowest gear is selected as a clock.
I Reset sequence
When a reset source is released, the CPU executes the following reset sequence:
(000FFFFC
Note:
After reset, the operating mode must be set via the mode register.
64
) --> PC
H
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