Table 3.6-1 System Clock Control Register (Sycc) Bits - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU

Table 3.6-1 System Clock Control Register (SYCC) Bits

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Instruction Cycle (tinst)
The instruction cycle (minimum instruction execution time) can be selected by the system clock
select bit (SCS) and main clock speed select bits (CS1 and CS0) in the system clock control
register (SYCC), from among the four different clock signals divide-by-4, 8, 16, 64, frequencies
obtained by dividing the oscillation frequency of the main clock and the subclock signal divide-
by-two (32.768 kHz).
At the highest speed (SYCC: SCS = "1", CS1, CS0= "11
cycle is 4 /F
66
Bit
• This bit checks the current clock mode (operating clock).
• When the bit is "0", the CPU is operating in subclock mode (with
SCM:
the main clock off or in oscillation stabilization delay state).
System
• When the bit is "1", the CPU is operating in main clock mode.
clock
Note:
monitor bit
This bit is read-only. Even if attempted to be written to the bit,
any value is meaningless and has no effect on operation.
• Any value read from either bit is indeterminate.
Unused bits
• Writing a value has no effect on operation.
• This pair of bits selects the main clock oscillation stabilization
delay time.
• The oscillation stabilization delay time selected by these bits is
taken when the CPU switches from subclock mode to main
clock mode and when it returns to normal operation from main-
WT1, WT0:
stop mode in response to an external interrupt.
Oscillation
• The initial values for the bits are selected by option settings.So,
stabilization
the oscillation stabilization delay time taken at a reset is the
delay time
oscillation stabilization delay time selected by the option.
select bits
Note:
Do not rewrite these bits upon switching from the subclock to
main clock (SCS = "1" --> "0"). Before rewriting them, use the
SCM bit to check that the CPU is not currently in the main clock
oscillation stabilization delay state.
• This bit specifies the clock mode.
• Writing "0" to the bit switches the CPU from main clock mode to
subclock mode.
SCS:
• Writing "1" to the bit switches the CPU from subclock mode to
System
main clock mode after taking the oscillation stabilization delay
clock select
time set by the WT1 and WT0 bits.
bit
Note:
When the single-clock option has been selected, this bit is
meaningless. Always set the bit to "1".
This pair of bits selects the clock speed used in main clock mode.
CS1, CS0:
These bits can select one of the four different speeds for the
Main clock
operating clock for the CPU and peripherals (using the clock gear
speed select
function). The settings of the bits have nothing to do with the
bits
operating clocks for timebase timer and watch prescaler.
= approx. 0.95 µs at a main clock oscillation (F
CH
Function
") in main clock mode, the instruction
B
) of 4.2 MHz.
CH