Watchdog Timer Control Register (Wdtc); Fig. 9.2 Watchdog Timer Control Register (Wdtc); Table 9-1 Ponr, Stbr, Wrst, Erst, Srst (Reset Factor Bits) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

9.3.1 Watchdog Timer Control Register (WDTC)

The watchdog timer control register (WDTC) starts and clears the watchdog time, and displays the reset
factor.
n Watchdog timer control register (WDTC)
Watchdog control register
Address: 0000A8
H
Read/write →
Initial value →
Note: Access by read-modify family instructions causes a malfunction, so do not access by these
instructions.
[bits 7 to 3] PONR, WRST, ERST, SRST
PONR, WRST, ERST, and SRST are flags indicating reset factors. These flags are set by each reset as
shown in Table 9-1. After reading the WDTC register, all bits are cleared to 0.
These bits are for read-only registers. Note that the values of bits indicating sources (reset factors)
except at power-on are not assured. So, create the software so as to ignore other bits when the PONR
bit is 1.

Table 9-1 PONR, STBR, WRST, ERST, SRST (Reset Factor Bits)

External pin (RSTX input)
RST bit (software reset)
*: The previous value is held.
This register value is not assured when power is risen when no power-on reset occurs.
[bit 2] WTE
When 0 is written to WTE when the watchdog timer is stopped, the watchdog timer enters the operating
state. When 0 is written to WTE for the second or later time, the watchdog timer counter is cleared.
When 1 is written to WTE, the watchdog timer is unaffected.
The watchdog timer is set to the stop state at various reset factors. At reading, 1 is read from WTE.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
7 6 5
—
PONR WRST
(R) (—) (R)
(X) (—) (X)

Fig. 9.2 Watchdog Timer Control Register (WDTC)

Reset Factor
Power-on
Watchdog timer
4 3
ERST SRST WTE
(R) (R) (W)
(X) (X) (1)
PONR WRST
1 —
* 1
* *
* *
9-6
← Bit No.
2 1 0
WT1 WT0
(W) (W)
(1) (1)
ERST SRST
— —
* *
1 *
* 1
WDTC