Table 3.7.3 Standby Control Register (Stbc) Bits - Fujitsu F2MC-8L MB89620 Series Hardware Manual

Table 3.7.3 Standby Control Register (STBC) Bits

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MB89620 series
Bit
•
Sets the CPU changing to stop mode.
•
Writing "1" to this bit sets the CPU changing to stop mode.
STP:
Stop bit •
Writing "0" to this bit has no effect on operation.
•
Reading this bit always returns "0".
•
Sets the CPU changing to sleep mode.
•
Writing "1" to this bit sets the CPU changing to sleep mode.
SLP:
Sleep bit •
Writing "0" to this bit has no effect on operation.
•
Reading this bit always returns "0".
•
Specifies the states of the external pins during stop mode.
•
Writing "0" to this bit specifies that external pins hold their states (levels) on
SPL:
changing to stop mode.
Pin state
•
Writing "1" to this bit specifies that external pins go to high-impedance state on
specification bit
entering stop mode. (Pins with a pull-up resistor (optional) go to the "H" level.)
•
Initialized to "0" by a reset.
•
Specifies a software reset.
RST:
•
Writing "0" to this bit generates an internal reset source for four instruction cycles.
Software reset
•
Writing "1" to this bit has no effect on operation.
bit
•
Reading this bit always returns "1".
•
The read value is indeterminate.
Unused bits
•
Writing to these bits has no effect on operation.
Function
CHAPTER 3 CPU
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