Intel altera Agilex 7 User Manual
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Intel altera Agilex 7 User Manual

Intel altera Agilex 7 User Manual

Fpga i-series transceiver (6xf-tile) development kit
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(6 × F-Tile) Development Kit User
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7 FPGA I-Series Transceiver
776646
2024.11.21

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Summary of Contents for Intel altera Agilex 7

  • Page 1 Explore more resources ® Altera Design Hub ™ Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide 776646 Online Version Send Feedback 2024.11.21...

  • Page 2: Table Of Contents

    2.3.1. Installing the Quartus Prime Pro Edition Software...........8 2.3.2. Installing the Intel SoC EDS................ 8 2.3.3. Installing the Development Kit..............9 2.3.4. Installing the Intel FPGA Download Cable II Driver........10 3. Development Kit Setup....................11 3.1. Default Settings....................11 3.2. Powering Up the Development Kit................12 3.3.
  • Page 3 Contents 7. Document Revision History for the Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide..................42 A. Development Kit Components..................43 A.1. Board Overview and Components................43 A.1.1. Board Overview..................43 A.1.2. Board Components...................44 A.2. System Management....................45 A.3.

  • Page 4: Overview

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Block Diagram

    1. Overview 776646 | 2024.11.21 1.1. Block Diagram Figure 2. Agilex 7 FPGA I-Series Transceiver Development Kit Block Diagram Type-B UBII/PWR MAX® 10 DDR4 x5 SDM DC JTAG FPGA (MT40A2G16SKL) PWR_MAX10_I2C JTAG Avalon Streaming x16 Hyper RAM System Flash 2GB x2 DIFF (x34) GPIOs MAX 10...

  • Page 6: Box Contents

    1. Overview 776646 | 2024.11.21 • F-Tile 5 (13B): — 4 FGT Transceiver to channels to Mini Cool Edge IO (MCIO) — 8 FGT transceiver channels to QSFP-DD connector — 4 FHT transceiver channels fan out to Octal Small Form Factor Pluggable (OSFP) connector •...

  • Page 7: Getting Started

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 8: Installing The Quartus Prime Pro Edition Software

    SoC embedded systems. As a part of the Intel SoC EDS, the Arm* Development Studio 5 (DS-5) Intel SoC FPGA Edition Toolkit provides a comprehensive set of embedded development tools for Altera's SoC FPGAs.

  • Page 9: Installing The Development Kit

    Agilex 7 FPGA I-Series Transceiver Development Kit webpage on the Intel website. 2. Unzip the Agilex 7 FPGA I-Series Transceiver Development Kit installer package. The package creates the directory structure shown in the figure below. Figure 3.

  • Page 10: Installing The Intel Fpga Download Cable Ii Driver

    Installation instructions for the Intel FPGA Download Cable driver for your operating system are available on the Intel website. On the Intel website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions.

  • Page 11: Development Kit Setup

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 12: Powering Up The Development Kit

    2. Attach the system MAX 10 image on the system MAX 10 part. 3. Select programming options and click Program button. Note: Once you plug Intel FPGA Download Cable between J11 and PC, the on-board Intel FPGA Download Cable circuit is disabled automatically. ™...

  • Page 13: Restoring Board Qspi Flash With The Default Factory Image

    3. Development Kit Setup 776646 | 2024.11.21 3.3.2. Restoring Board QSPI Flash with the Default Factory Image 1. Plug the QSPI flash card into the J3 slot. 2. Ensure that are [ON/ON/OFF] (Avalon streaming interface x8 MSEL[2:0] configuration mode) before powering up the board. 3.

  • Page 14: Board Test System

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 15: Setting Up The Bts Gui Running Environment

    4. Board Test System 776646 | 2024.11.21 4.1. Setting Up the BTS GUI Running Environment To run BTS GUI, including the Power Monitor and Clock Controller GUI, you must download and install Java runtime including OpenJDK and OpenJFX on your systems and set up the running environment.

  • Page 16: Setting Up The Quartus Prime Software For Bts Operation

    4. Board Test System 776646 | 2024.11.21 Note: The unzipped folder name of JRE is (for example, jdk-11.0.xx+x-jre ), and you must rename it to . The unzipped jdk-11.0.14+9-jre folder name of JFX is , and you must rename it to javafx-sdk-17.0.2 2.
  • Page 17 4. Board Test System 776646 | 2024.11.21 Note: To ensure operating stability, keep the USB cable connected and the board powered on when running the demonstration application. You must attach the USB cable and power on the board for BTS to run correctly. Navigate to the directory to run <packagedir>\examples\board_test_system...

  • Page 18: Bts Functionalities

    4. Board Test System 776646 | 2024.11.21 4.2. BTS Functionalities This section describes each control in the BTS. 4.2.1. The Bottom Info Bar The bottom information bar shows the status of the system connection, the Quartus Prime version and the JTAG clock. •...

  • Page 19: The Sys Info Tab

    4. Board Test System 776646 | 2024.11.21 To configure the FPGA with a test system design, follow these steps: 1. On the Configure menu, click the Configure command that corresponds to the functionality you want to test. 2. In the dialog box that appears, click Configure to download the corresponding design's SRAM Object File ( ) to the FPGA.

  • Page 20: Board Information

    4. Board Test System 776646 | 2024.11.21 Board Information The board information control displays static information about your board. • Board Name: Indicates the official name of the board given by the BTS. • Board Revision: Indicates the revision of the board. •...

  • Page 21: The Xcvr Tab

    4. Board Test System 776646 | 2024.11.21 User LEDs The User LEDs control displays the current state of the user LEDs. Toggle the LED buttons to turn the board LEDs on and off. Click the All button to reverse the state of all the LEDs.
  • Page 22 4. Board Test System 776646 | 2024.11.21 Figure 12. The QSFPDD-23 NRZ Tab The following sections describe controls in the QSFPDD NRZ tab. Status The Status control displays the following status information during the loopback test: • PLL Lock: Shows the PLL locked or unlocked state. •...

  • Page 23: Pma Setting

    4. Board Test System 776646 | 2024.11.21 • QSFPDD0 x8 • QSFPDD1 x8 • QSFPDD2 x8 • QSFPDD3 x8 PMA Setting The PMA Setting control allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis: •...

  • Page 24: Error Control

    4. Board Test System 776646 | 2024.11.21 Error Control This control displays data errors detected during analysis and allows you to insert errors: • Detected Errors: Displays the number of data errors detected in the received bit stream. • Inserted Errors: Displays the number of errors inserted into the transmit data stream.
  • Page 25 4. Board Test System 776646 | 2024.11.21 4.2.5.2. The FMCA NRZ Tab Similar control functions with the QSFPDD NRZ tab except for the port selection. Figure 16. The FMCA NRZ Tab ™ Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide Send Feedback...
  • Page 26 4. Board Test System 776646 | 2024.11.21 4.2.5.3. The FMCB NRZ Tab Similar control functions with the QSFPDD NRZ tab except for the port selection. Figure 17. The FMCB NRZ Tab ™ Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide Send Feedback...
  • Page 27 4. Board Test System 776646 | 2024.11.21 4.2.5.4. The QSFPDD400/QSFPDD800 PAM4 Tab Similar control functions with the QSFPDD NRZ tab except for the port selection. DK- SI-AGI040FES has QSFP-DD400 PAM4, while DK-SI-AGI040EA has QSFP-DD800 PAM4. Figure 18. The QSFPDD400/QSFPDD800 PAM4 Tab ™...
  • Page 28 4. Board Test System 776646 | 2024.11.21 4.2.5.5. The QSFP NRZ Tab Similar control functions with the QSFPDD NRZ tab except for the port selection. Figure 19. The QSFP NRZ Tab ™ Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide Send Feedback...
  • Page 29 4. Board Test System 776646 | 2024.11.21 4.2.5.6. The SFP Tab Similar control functions with the QSFPDD NRZ tab. Figure 20. The SFP Tab ™ Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide Send Feedback...
  • Page 30 4. Board Test System 776646 | 2024.11.21 4.2.5.7. The OSFP Tab Similar control functions with the QSFPDD NRZ tab. Figure 21. The OSFP Tab ™ Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide Send Feedback...

  • Page 31: The Memory Tab

    4. Board Test System 776646 | 2024.11.21 4.2.6. The Memory Tab This tab allows you to read and write DDR4-COMP and DDR4-RDIMM memory on your board. Download the design through the BTS Configure menu. Figure 22. The COMP Tab The following sections describe controls on this tab. Start Initiates DDR4 memory transaction performance analysis.

  • Page 32: Performance Indicators

    4. Board Test System 776646 | 2024.11.21 Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start: • Write and Read performance bars: Show the percentage of maximum theoretical data rate that the requested transactions can achieve. •...
  • Page 33 4. Board Test System 776646 | 2024.11.21 Figure 23. The RDIMM Tab Same with DDR4-COMP. ™ Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide Send Feedback...

  • Page 34: Control On-Board Clock Through Clock Controller Gui

    4. Board Test System 776646 | 2024.11.21 4.3. Control On-Board Clock through Clock Controller GUI The Clock Controller GUI can change the on-board Si5391/Si5395-1/Si5395-2/Si5518. The instructions to run Clock Controller GUI are stated in the Running the BTS GUI page 16. Alternatively, you can start using the Clock Controller feature by selecting the Clock icon on the BTS GUI.
  • Page 35 4. Board Test System 776646 | 2024.11.21 Import Si5391 has a two-time rewritable non-volatile memory (NVM). You can generate the register list from the Skyworks* ClockBuilder Pro tool and import it into Si5391 to update the settings of the RAM. Register changes are volatile after power cycling. Figure 25.

  • Page 36: Soft Reset

    4. Board Test System 776646 | 2024.11.21 Figure 27. Si5518 Import You can generate the register list from the ClockBuilder Pro tool and import it into Si5518 to update the settings of RAM. Register changes are volatile after power cycling. Default Sets the frequency for the oscillator associated with the active tab back to its default value.

  • Page 37: Monitor On-Board Power Regulator Through Power Monitor Gui

    4. Board Test System 776646 | 2024.11.21 4.4. Monitor On-Board Power Regulator through Power Monitor GUI The Power Monitor GUI reports most power rails’ voltage, current, and power information on the board. It also collects temperature from FPGA die, power modules, and diodes assembled on PCB.

  • Page 38: Identify Test Pass Or Fail-Based On Bts Gui Test Status

    4. Board Test System 776646 | 2024.11.21 Figure 29. Power Monitor GUI—The Temperature Tab Temperature Reads the temperature data from temperature sense diodes inside the FPGA die or assembled on PCB. Local Temp Shows the temperature comparison of local and remote temperature sensors. Beta Comp Enables beta compensation for temperature sensing chips.
  • Page 39 4. Board Test System 776646 | 2024.11.21 QSFP Plug QSFP loopback module in J57/J58/J66 before you configure QSFP NRZ example build through BTS GUI. OSFP Plug OSFP loopback module in J45 before you configure OSFP NRZ example build through BTS GUI. Plug four SFP loopback modules in J77 before you configure SFP NRZ example build through BTS GUI.

  • Page 40: Development Kit Hardware And Configuration

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 41: Custom Projects For The Development Kit

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 42: Document Revision History For The Agilex 7 Fpga I-Series Transceiver (6 × F-Tile) Development Kit User Guide

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 43: Development Kit Components

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 44: Board Components

    A. Development Kit Components 776646 | 2024.11.21 A.1.2. Board Components Table 6. Board Connector/Switch Description Connector/Switch Description 12 V AUX1 connector 12 V AUX2 connector SDM connector FAN0 connector (Core FET fan) FMCA connector FMCB connector QSFP0 connector QSFP-DD0 connector QSFP-DD800 connector QSFP1 connector QSFP-DD1 connector...

  • Page 45: System Management

    JTAG controller: Manage JTAG chain topology, JTAG master source and JTAG slaves by S19. Table 7. JTAG Master Sources Schematic Signal Name Description JTAG header J11 for Intel FPGA Download Cable EXT_JTAG_TCK/TDO/TMS/TDI Input port J10 for on-board Intel download circuit FX2_Dp/n Mode S20[4:1]...
  • Page 46 On: bypass from chain Off: enable in chain S19.1 (HPS) Chained HPS with SDM nodes externally. S19.2 (SysMax) Mode 4: External Intel FPGA Download Cable act as the only JTAG Master. S19.3(FMC_B) Chained HPS with SDM node externally. S19.4 (FMC_A) ON/OFF/ON S19.1 (SDM+HPS)

  • Page 47: Power

    A. Development Kit Components 776646 | 2024.11.21 A.3. Power Figure 31. Power Tree P1V8_G3_EN FPGA VCCIO_SDM / VCCBAT/ +P1V8_G3 ADP7159 VCCFUSEWR_SDM 1.007A@1.8V Daughter cards +P2V5_G2 DDR4 DIMM/COMP LT M4657 P2V5_G2_EN CLK_MUX 3.653A.@2.5V +VCCEHT_FHT_GXF_1V5_U1x_G2 ADP7159 FPGA VCCEHT_U1x_P1V5_G2_EN VCCEHT_FHT_GXF_U1x 0.8A@1.5V +VCCEHT_FHT_GXF_1V5_U2x_G2 FPGA ADP7159 VCCEHT_U2x_P1V5_G2_EN VCCEHT_FHT_GXF_U2x...

  • Page 48: Clocks

    A. Development Kit Components 776646 | 2024.11.21 Figure 32. Power Sequence On board hot-plug circuit shuts down all power rails when total power over 360 W (30 A) @ each power port. UB2/PWR MAX 10 shuts down significant power rails when one or more power good indicators below low due to a power fault.
  • Page 49 A. Development Kit Components 776646 | 2024.11.21 Schematic Signal Name Default Frequency (Hz) DDR_1_166.66M_REFCLK_DN/DP 166.66M DDR_2_166.66M_REFCLK_DN/DP 166.66M DDR_3_166.66M_REFCLK_DN/DP 166.66M DDR_4_166.66M_REFCLK_DN/P 166.66M CLK_100M_GPIO_2C_DN/DP 100M 1PPS_SMA_OUT_1V2 CLK_100M_GPIO_4_DN/DP 100M CLK_PCIE_EP_MCIO1_DP/DN 100M CLK_PCIE_RP_MCIO1_DP/DN 100M PCIE_100M_REF_AP/AN 100M SYS_M10_50M PWR_M10_50M SMA_1PPS_OUT SMA_10MHZ_OUT REFCLK_FGT_12A_8_DP/DP Not assigned REFCLK_FGT_12A_9_DP/DP Not assigned FMCA_RECRD_CLK_DP/DN Not assigned...
  • Page 50 OUT-2 I2C/SPI REFCLK-2 [GC] REFCLK-1 156.25M-SPARE OUT-3 CTRL/STAT REFCLK-3 [GC] 156.25M REFCLK-2 [GC] 156.25M-SPARE REFCLK-3 [GC] rp_refout REFCLK Intel Agilex 7 FPGA I-Series AGIC040R39A pcie_ep_refin ™ Agilex 7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User Guide Send Feedback...

  • Page 51: General Input/Output

    A. Development Kit Components 776646 | 2024.11.21 A.5. General Input/Output Table 9. MAX 10 and FPGA Schematic Signal Name Description The value of the filtered F_GPIO0 user_pb[0] The value of the filtered F_GPIO1 user_pb[1] Reserved F_GPIO2 Reserved F_GPIO3 Reserved F_GPIO4 Reserved F_GPIO5 Reserved...
  • Page 52 A. Development Kit Components 776646 | 2024.11.21 Schematic Signal Name Description User LED USER_LED3 User LED USER_LED4 User LED USER_LED5 User LED USER_LED6 User LED USER_LED7 The value of the filtered F_GPIO0 user_pb[0] The value of the filtered F_GPIO1 user_pb[1] MCIO_PERST in RP mode F_GPIO2 FMC_A_PERST in RP mode...
  • Page 53 A. Development Kit Components 776646 | 2024.11.21 Schematic Signal Name Description MAX_CONF_DONE for Avalon streaming configuration SYS_LED3/D12 Reserved SYS_LED5/D14 Reserved SYS_LED7/D16 MAX_RESETn SYS_PB0/S11 FPGA_RESETn SYS_PB1/S12 Power recycle SYS_PB2/S14 PGM_SEL for Avalon streaming configuration SYS_PB3/S16 PGM_CFG for Avalon streaming configuration SYS_PB4/S17 Fan 2 PWM signal FPGA_FAN_PWM Fan 2 tachometer signal...
  • Page 54 A. Development Kit Components 776646 | 2024.11.21 Schematic Signal Name Description Driven low R_12C_PERST_IO_N Do not use (DNU) SI5395_1_A_IN_SEL0_R High before system power OK SI5395_2_A_OEN_SYS_R Low after system power OK Tied to system power OK SI52204_PWRGD_R SI5395_2_A_IN_SEL0_R High before system power OK SI5395_1_A_OEN_SYS_R Low after system power OK High before system power OK...

  • Page 55: Memory Interfaces

    A. Development Kit Components 776646 | 2024.11.21 Table 11. UB2/PWR MAX 10 Schematic Signal Name Description FPGA Power Good FPGA_POK_LED Reserved GPIO between system MAX 10 and power MAX 10 SYS_PWR_RSV0 Reserved GPIO between system MAX 10 and power MAX 10 SYS_PWR_RSV1 Reserved GPIO between system MAX 10 and power MAX 10 SYS_PWR_RSV2...
  • Page 56 A. Development Kit Components 776646 | 2024.11.21 QSFPDD Agilex 7 FPGA I-Series Transceiver Development Kit supports 4x QSFPDD ports. The QSFPDD port fans out from the Agilex 7 I-Series FPGA F-Tile (FGT). All 8 channels per QSFPDD can run up to 25 Gbps NRZ and 50 Gbps PAM4. Table 13.
  • Page 57 A. Development Kit Components 776646 | 2024.11.21 Schematic Signal Names Description C data I2C_QSFP_2_SDA Transceiver TX QSFPDD2_TX_[0:7]_DP/DN Transceiver RX QSFPDD2_RX_[0:7]_DP/DN Table 16. QSFPDD Connector -3 (13B/J67) Schematic Signal Names Description Module present QSFPDD3_3V3_MODPRS_L Module reset QSFPDD3_3V3_RESET_L Mode select QSFPDD3_3V3_MODSEL_L Initial mode QSFPDD3_3V3_LPMODE Interrupt QSFPDD3_3V3_INT_L...
  • Page 58 A. Development Kit Components 776646 | 2024.11.21 QSFP Agilex 7 FPGA I-Series Transceiver Development Kit supports 3x QSFP ports. The QSFP port fans out from the Agilex 7 I-Series FPGA F-Tile (FGT). All 4 channels can run up to 1 Gbps per lane. Table 18.
  • Page 59 A. Development Kit Components 776646 | 2024.11.21 Schematic Signal Names Description C data I2C_QSFP_2_SDA Transceiver TX QSFP2_TX_[0:3]_DP/DN Transceiver RX QSFP2_RX_[0:3]_DP/DN OSFP Agilex 7 FPGA I-Series Transceiver Development Kit supports OSFP ports. OSFP port fans out from the Agilex 7 I-Series FPGA F-Tile (FHT). The FHT Tile from bank 13B and 13C can run up to 400 Gbps (50G x 8) PAM4 in DK-SI-AGI040FES.
  • Page 60 A. Development Kit Components 776646 | 2024.11.21 Schematic Signal Names Description SFP2_RATE_SEL Module Rate Select 0 SFP2_MOD1_PRSNT_N Module Present SFP2_LOS Loss of Signal SFP2_TX_FAULT Transmitter Fault Indication SFP2_RS1 Module rate select 1 SFP2_MOD1_SCL C clock SFP2_MOD1_SDA C data SFP2_TX_DP/DN Transceiver TX SFP2_RX_DP/DN Transceiver RX SFP1_TX_DISABLE...
  • Page 61 A. Development Kit Components 776646 | 2024.11.21 Serial Buses SDM I/Os ( ) and MAX 10 I/Os ( ) share the same I C bus SDM_IO0/12 VCCL_SDA/SCL which talks with Agilex 7 FPGA core regulators. By default, SDM acts as SmartVID master and system MAX 10 act as Power GUI master in this chain.

  • Page 62: Daughter Cards

    Level SFP1_I2C Shifter @1.2V @3.3V FMC+ PCA95351_1_I2C Connector-A (J7) @3.3V Level SFP2 Shifter @3.3V @1.2V @3.3V FMC+ Level SFP2_I2C Intel Connector--B (J9) Shifter @1.2V @3.3V Level Agilex 7 SFP3 Shifter @3.3V @1.2V Level SFP3_I2C @3.3V FPGA MCIO Shifter @1.2V @3.3V...

  • Page 63: Developer Resources

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 64: Safety And Regulatory Compliance Information

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 65: Safety Warnings

    C. Safety and Regulatory Compliance Information 776646 | 2024.11.21 C.1.1. Safety Warnings Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system.

  • Page 66: Power Cord Requirements

    C. Safety and Regulatory Compliance Information 776646 | 2024.11.21 Power Cord Requirements The plug on the power cord must be a grounding-type male plug designed for use in your region. It must have certification marks showing certification by an agency in your region.

  • Page 67: Cooling Requirements

    C. Safety and Regulatory Compliance Information 776646 | 2024.11.21 Cooling Requirements Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan. Electro-Magnetic Interference (EMI) This equipment has not been tested for compliance with emission limits of FCC and similar international regulations.

  • Page 68: Electrostatic Discharge (Esd) Warning

    Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.

  • Page 69: Compliance Information

    C. Safety and Regulatory Compliance Information 776646 | 2024.11.21 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste.

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