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Intel Agilex User Manual

Intel Agilex User Manual

Variable precision dsp blocks
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UG-20213 | 2019.04.02
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  • Page 1 ® ™ Intel Agilex Variable Precision DSP Blocks User Guide Subscribe UG-20213 | 2019.04.02 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    3.2.1. FP32 Single-Precision Floating-Point Arithmetic Functions......40 3.2.2. FP16 Half-Precision Floating-Point Arithmetic Functions......... 44 3.2.3. Multiple Floating-Point Variable DSP Blocks Functions........55 4. Intel Agilex Variable Precision DSP Blocks Design Considerations........ 62 4.1. Fixed-Point Arithmetic..................62 4.1.1. Configurations for Input, Pipeline, and Output Registers........ 62 4.1.2.
  • Page 3 Contents 5. Document Revision History for the Intel Agilex Variable Precision DSP Blocks User Guide........................73 ® ™ Intel Agilex Variable Precision DSP Blocks User Guide Send Feedback...

  • Page 4: Intel ® Agilex ™ Variable Precision Dsp Blocks Overview

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Supported Operational Modes In Intel Agilex Devices

    • Subnormal values handling Related Information Intel Agilex Device Data Sheet—DSP Block Specifications Refer to the Intel Agilex Device Data Sheet for more information on the DSP block performance. 1.2. Supported Operational Modes in Intel Agilex Devices 1.2.1. Fixed-Point Arithmetic Table 1.
  • Page 6 Related Information • Intel Agilex Device Overview—Intel Agilex FPGAs Family Plan Refer to the Intel Agilex FPGAs Family Plan in the Intel Agilex Device Overview for more information on the variable precision DSP blocks resources. • Pre-adder for Fixed-Point Arithmetic on page 17 •...

  • Page 7: Floating-Point Arithmetic

    ® ™ 1. Intel Agilex Variable Precision DSP Blocks Overview UG-20213 | 2019.04.02 1.2.2. Floating-Point Arithmetic Table 3. Supported Combinations of Operational Modes and Features Variable-Precision Operation Mode Supported Chainin Support Chainout Support DSP Block Resource Operation Instance 1 variable precision...
  • Page 8 Related Information • Intel Agilex Device Overview—Intel Agilex FPGAs Family Plan Refer to the Intel Agilex FPGAs Family Plan in the Intel Agilex Device Overview for more information on the variable precision DSP blocks resources. • Operational Modes for Floating-Point Arithmetic on page 40 •...

  • Page 9: Intel Agilex Variable Precision Dsp Blocks Architecture

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 10 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 1. Fixed-Point Arithmetic 9 x 9 Mode chainin[63..0] ENA[2..0] CLR[1..0] DISABLE_CHAINOUT LOADCONST ACCUMULATE 1st Multiplier ay[8..0] Constant 1st Adder ax[8..0] by[8..0] bx[8..0] 2nd Multiplier Double 3rd Multiplier Accumulation cy[8..0]...
  • Page 11 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 2. Fixed-Point Arithmetic 18 x 19 Mode scanin[18..0] chainin[63..0] ENA[2..0] CLR[1..0] DISABLE_CHAINOUT DISABLE_SCANIN LOADCONST ACCUMULATE NEGATE Pre-Adder **Systolic **Systolic Constant Registers Multiplier Register ay[18..0] az[17..0] ax[17..0] COEFSELA[2..0] Internal...

  • Page 12: Fixed-Point Arithmetic

    2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 4. Floating-Point Arithmetic 16-bit Half-Precision Mode fp32_chainin[31:0] accumulate *Pipeline *Pipeline *Pipeline Register Register Register Adder Input fp32_adder_a[31:0] Output fp32_result[31:0] Register Register fp16_mult_top_invalid Bank Bank fp16_mult_top_inexact fp16_mult_top_a[15:0] fp16_mult_top_overflow fp16_mult_top_underflow...
  • Page 13 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 • Data • Dynamic control signals — NEGATE — LOADCONST — ACCUMULATE — SUB — Dynamic Scanin — Dynamic Chainout All the registers in the DSP blocks are positive-edge triggered and cleared on power up.
  • Page 14 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 6. Data Input Registers in Fixed-Point Arithmetic 9 x 9 Mode ENA[2..0] CLR[0] ay[8..0] ax[8..0] by[8..0] by[8..0] cy[8..0] cx[8..0] dy[8..0] dx[8..0] ® ™ Intel Agilex Variable Precision DSP Blocks User Guide...
  • Page 15 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 7. Data Input Registers in Fixed-Point Arithmetic 18 x 19 Mode ENA[2..0] scanin[18..0] CLR[0] ay[18..0] az[17..0] ax[17..0] Top delay registers by[18..0] bz[17..0] bx[17..0] Bottom delay registers scanout[18..0] ®...

  • Page 16: Pipeline Registers For Fixed-Point Arithmetic

    2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 8. Data Input Registers in Fixed-Point Arithmetic 27 x 27 Mode ENA[2..0] scanin[26..0] CLR[0] ay[26..0] az[25..0] ax[26..0] scanout[26..0] Related Information Configurations for Input, Pipeline, and Output Registers on page 62 Provides information about restrictions on fixed-point arithmetic input registers.

  • Page 17: Pre-Adder For Fixed-Point Arithmetic

    (either addition or subtraction). 2.1.4. Internal Coefficient for Fixed-Point Arithmetic The Intel Agilex variable precision DSP block has the flexibility of selecting the multiplicand from either the dynamic input or the internal coefficient. The internal coefficient can support up to eight constant coefficients for the multiplicands in 18-bit and 27-bit modes.

  • Page 18: Accumulator, Chainout Adder, And Preload Constant For Fixed-Point Arithmetic

    2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic The Intel Agilex variable precision DSP block supports accumulator and adder up to 64 bits for fixed-point arithmetic. The following signals can dynamically control the function of the accumulator and the chainout adder: •...

  • Page 19: Systolic Register For Fixed-Point Arithmetic

    2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 9. Dynamic Chainout Input disable_chainout register Output register chainout 64’b0 Table 8. DISABLE_CHAINOUT Signal Behavior DISABLE_CHAINOUT Signal Description Low (0) Chainout = result from output register High (1) Chainout = 0.

  • Page 20: Output Register Bank For Fixed-Point Arithmetic

    2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 If the double accumulation register is enabled, an extra clock cycle delay is added into the feedback path of the accumulator. This register has the same settings as the output register bank.
  • Page 21 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 10. Location of Input Register for FP32 Operation Modes fp32_chainin[31:0] accumulate *Pipeline *Pipeline Register Register Adder Output fp32_adder_a[31:0] fp32_result[31:0] Register fp32_mult_invalid Bank fp32_mult_inexact fp32_adder_b[31:0] fp32_mult_overflow fp32_mult_underflow fp32_mult_a[31:0] fp32_adder_invalid...

  • Page 22: Pipeline Registers For Floating-Point Arithmetic

    2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Related Information Configurations for Input, Pipeline, and Output Registers on page 67 Provides information about restrictions on floating-point arithmetic input registers. 2.2.2. Pipeline Registers for Floating-Point Arithmetic Floating-point arithmetic has 3 latency layers of pipeline registers. You can bypass all latency layers of the pipeline registers or use any one, two or three layers of pipeline registers.

  • Page 23: Multipliers For Floating-Point Arithmetic

    2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Figure 13. Location of Pipeline Register for FP16 Operation Modes fp32_chainin[31:0] accumulate Adder Input fp32_adder_a[31:0] Output Register fp32_result[31:0] Register fp16_mult_top_invalid Bank Bank fp16_mult_top_inexact fp16_mult_top_a[15:0] fp16_mult_top_overflow fp16_mult_top_underflow fp16_mult_top_b[15:0] Adder fp16_mult_top_infinite...

  • Page 24: Adder Or Subtractor For Floating-Point Arithmetic

    2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 2.2.4. Adder or Subtractor for Floating-Point Arithmetic Depending on the operational mode, you can use the adder or subtractor as • A single precision addition/subtraction • A single-precision multiplication with addition/subtraction •...

  • Page 25: Exception Handling For Floating-Point Arithmetic

    Configurations for Input, Pipeline, and Output Registers on page 67 Provides information about restrictions on floating-point arithmetic output registers. 2.2.6. Exception Handling for Floating-Point Arithmetic The Intel Agilex floating-point arithmetic supports exception handling for the multiplier and adder blocks. Table 9. Supported Exception Flags Floating-...
  • Page 26 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Floating- Exception Flags Width Description Point Format 1: If the multiplier result is a smaller value than the minimum representable non-zero absolute value and the result is flushed to zero.
  • Page 27 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Floating- Exception Flags Width Description Point Format 1: If the multiplier result is a larger value than the maximum representable value and the result is cast to infinity. 0: If the multiplier result is smaller than the maximum presentable value.
  • Page 28 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Floating- Exception Flags Width Description Point Format 0: If the adder result is a larger than the minimum representable value. This signal is not available in Multiplication Mode Extended format.
  • Page 29 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Input A Input B Result Flags Overflow/Underflow/ Inexact/Invalid Positive/negative infinity 0 or Subnormal (denormal) qNaN value 0/0/0/1 Quiet Not A Number (qNaN) 0 or Subnormal (denormal) qNaN value 0/0/0/0...
  • Page 30 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Input A Input B Result : Flags Overflow/Underflow/ Inexact/Invalid • Positive infinity value + positive infinity value • Negative infinity value + negative infinity value • Negative infinity value - positive infinity value •...
  • Page 31 2. Intel Agilex Variable Precision DSP Blocks Architecture UG-20213 | 2019.04.02 Input A Input B Result: Flags Infinite/Zero/Inexact/ Invalid Positive/negative infinity Normalized/Subnormalized Positive/negative infinity 1/0/0/0 value Quiet Not A Number (qNaN) Normalized/Subnormalized qNaN value 0/0/0/1 Mantissa = {100...00} 0 value...

  • Page 32: Intel Agilex Variable Precision Dsp Blocks Operational Modes

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 33 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 resultb = bx * by Figure 16. Two 18 × 18 or 18 × 19 Independent Multiplier per Variable Precision DSP Block In this figure, the variables are defined as follows: •...

  • Page 34: X 8 (Unsigned) Or 9 X 9 (Signed) Sum Of 4 Mode

    3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 3.1.2. 8 x 8 (unsigned) or 9 x 9 (signed) Sum of 4 Mode The 8 x 8 (unsigned) or 9 x 9 sum of 4 mode uses the following equations: resulta = (ax * ay)+(bx * by)+(cx * cy)+(dx * dy) Figure 18.

  • Page 35: Independent Complex Multiplier

    18 × 19 multiplications. 3.1.4. Independent Complex Multiplier The Intel Agilex devices support the 18 × 19 complex multiplier mode using two fixed- point arithmetic multiplier adder sum mode. Figure 20.
  • Page 36 The pipeline registers are embedded within the various circuits of the DSP block. 3.1.4.1. 18 × 19 Multiplication Summed with 36-Bit Input Mode Intel Agilex variable precision DSP blocks support one 18 × 19 multiplication summed to a 36-bit input.

  • Page 37: Systolic Fir Mode

    3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Figure 22. One 18 x 19 Multiplication Summed with 36-Bit Input Mode for Intel Agilex Devices In this figure, the variable is defined as follows: • n = 19 for 18 × 19 signed operands •...
  • Page 38 7 bits of overhead when using an 18 x 19 operation mode, resulting 37-bit result. This allows a total sixteen 18 x 19 multipliers or eight Intel Agilex variable precision DSP blocks to be cascaded as systolic FIR structure.
  • Page 39 In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing 10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of eleven 27 x 27 multipliers or eleven Intel Agilex variable precision DSP blocks to be cascaded as systolic FIR structure.

  • Page 40: Operational Modes For Floating-Point Arithmetic

    3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 3.2. Operational Modes for Floating-Point Arithmetic 3.2.1. FP32 Single-Precision Floating-Point Arithmetic Functions The FP32 single-precision floating-point arithmetic DSP can perform the following: • FP32 multiplication • FP32 addition or subtraction •...
  • Page 41 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 The floating-point adder or subtract mode supports the following exception flags: • fp32_adder_invalid • fp32_adder_inexact • fp32_adder_overflow • fp32_adder_underflow Figure 29. Adder or Subtract Mode for Intel Agilex...
  • Page 42 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Figure 30. Multiply Accumulate Mode for Intel Agilex Devices fp32_chainin[31:0] accumulate *Pipeline *Pipeline Register Register *Pipeline Bank Bank Adder Register Input fp32_adder_a[31:0] Bank Output Register fp32_result[31:0] fp32_adder_b[31:0] Register...
  • Page 43 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Figure 31. Vector One Mode fp32_chainin[31:0] accumulate *Pipeline *Pipeline Register Register *Pipeline Bank Bank Adder Register Input Bank Output fp32_adder_a[31:0] Register fp32_result[31:0] Register Bank fp32_adder_b[31:0] Bank fp32_mult_invalid fp32_mult_inexact...

  • Page 44: Fp16 Half-Precision Floating-Point Arithmetic Functions

    3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Figure 32. FP32 Vector Two Mode fp32_chainin[31:0] accumulate *Pipeline *Pipeline Register Register *Pipeline Bank Bank Adder Register Input Output Bank fp32_adder_a[31:0] Register Register fp32_result[31:0] Bank fp32_adder_b[31:0] Bank fp32_mult_invalid...
  • Page 45 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Table 18. Differences between Flushed, Extended, and Bfloat Formats Features Flushed Extended Bfloat16/Bfloat 16+ Input format 1.5.10 1.5.10 1.8.7 or 1.8.10 (Bfloat16+) (sign.exponent.mantissa) FP16 operation format 1.5.10 1.8.10 1.8.10...
  • Page 46 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 • fp16_mult_bot_invalid • fp16_mult_bot_inexact • fp16_mult_bot_overflow • fp16_mult_bot_underflow • fp16_adder_invalid • fp16_adder_inexact • fp16_adder_overflow • fp16_adder_underflow The following are exception flags supported in extended format: • fp16_mult_top_invalid •...
  • Page 47 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode This mode performs a summation of two half-precision multiplication, provide a 32-bit result, and add with a single-precision number:...
  • Page 48 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 • fp32_adder_inexact • fp32_adder_overflow • fp32_adder_underflow Figure 34. Sum of Two FP16 Multiplication with FP32 Addition Mode fp32_chainin[31:0] *Pipeline *Pipeline *Pipeline Register Register Register Adder Input fp32_result[31:0] fp32_adder_a[31:0]...
  • Page 49 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 • fp32_adder_inexact • fp32_adder_overflow • fp32_adder_underflow The following are exception flags supported in extended format: • fp16_mult_top_invalid • fp16_mult_top_inexact • fp16_mult_top_infinite • fp16_mult_top_zero • fp16_mult_bot_invalid • fp16_mult_bot_inexact •...
  • Page 50 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 3.2.2.5. FP16 Vector One Mode This mode performs a summation of two half-precision multiplications with the chainin input from the previous variable DSP Block. The output is a single-precision floating- point value which is fed into chainout.
  • Page 51 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 • fp16_mult_bot_infinite • fp16_mult_bot_zero • fp16_adder_invalid • fp16_adder_inexact • fp16_adder_infinite • fp16_adder_zero • fp32_adder_invalid • fp32_adder_inexact • fp32_adder_overflow • fp32_adder_underflow Figure 36. FP16 Vector One Mode fp32_chainin[31:0] *Pipeline...
  • Page 52 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Chainin Parameter Vector Two with Floating-Point Vector Two with Floating-Point Addition Subtraction fp32_chainout = ( fp32_chainout = ( fp16_mult_top_a fp16_mult_top_a fp16_mult_top_b fp16_mult_top_b fp16_mult_bot_a fp16_mult_bot_a fp16_mult_bot_b fp16_mult_bot_b The following are exception flags supported in flushed and bfloat16 formats: •...
  • Page 53 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 • fp32_adder_inexact • fp32_adder_overflow • fp32_adder_underflow Figure 37. FP16 Vector Two Mode fp32_chainin[31:0] *Pipeline *Pipeline *Pipeline Register Register Register Adder Input fp32_adder_a[31:0] Output fp32_result[31:0] Register Register fp16_mult_top_invalid Bank...
  • Page 54 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 • fp16_mult_bot_inexact • fp16_mult_bot_overflow • fp16_mult_bot_underflow • fp16_adder_invalid • fp16_adder_inexact • fp16_adder_overflow • fp16_adder_underflow • fp32_adder_invalid • fp32_adder_inexact • fp32_adder_overflow • fp32_adder_underflow The following are exception flags supported in extended format: •...

  • Page 55: Multiple Floating-Point Variable Dsp Blocks Functions

    3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Figure 38. FP16 Vector Three Mode accumulate *Pipeline *Pipeline *Pipeline Register Register Register Adder Input fp32_adder_a[31:0] Output fp32_result[31:0] Register fp16_mult_top_invalid Register Bank fp16_mult_top_inexact Bank fp16_mult_top_a[15:0] fp16_mult_top_overflow fp16_mult_top_underflow fp16_mult_top_b[15:0]...
  • Page 56 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 • fp32_adder_inexact • fp32_adder_overflow • fp32_adder_underflow Figure 39. Multiply-Add or Multiply-Subtract Mode for Intel Agilex Devices fp32_chainin[31:0] accumulate *Pipeline *Pipeline Register Register *Pipeline Bank Bank Adder Register Input...
  • Page 57 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Figure 40. Direct Vector Dot Product Using FP32 Single-Precision Floating-Point Arithmetic Connect this signal to the fp32_chainout signal fp32_chainin[31:0] of the next DSP block in chain. accumulate *Pipeline...
  • Page 58 *This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block. 3.2.3.3. Complex Multiplication The Intel Agilex devices support the floating-point arithmetic single precision complex multiplier using four Intel Agilex variable-precision DSP blocks. Figure 42.
  • Page 59 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 The imaginary part [(a × d) + (b × c)] is implemented in the first two variable- precision DSP blocks, while the real part [(a × c) - (b × d)] is implemented in the next two variable-precision DSP blocks.
  • Page 60 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Figure 44. Complex Multiplication with Result Real Using FP32 Single-Precision Floating- Point Arithmetic fp32_chainin[31:0] accumulate *Pipeline *Pipeline Register Register *Pipeline fp32_adder_a[31:0] Bank Bank Adder Register Input fp32_adder_b[31:0] Bank...
  • Page 61 3. Intel Agilex Variable Precision DSP Blocks Operational Modes UG-20213 | 2019.04.02 Figure 46. Complex Multiplication with Result Real Using FP16 Half-Precision Floating- Point Arithmetic fp32_result[31:0] Result Real fp16_mult_top_a[15:0] Output fp16_mult_top_invalid Register fp16_mult_top_inexact Input fp16_mult_top_b[15:0] Bank Register fp16_mult_top_overflow Adder fp16_mult_top_underflow...

  • Page 62: Intel Agilex Variable Precision Dsp Blocks Design Considerations

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 63 4. Intel Agilex Variable Precision DSP Blocks Design Considerations UG-20213 | 2019.04.02 • When the pipeline registers for signals are enabled, LOADCONST ACCUMULATE the pipeline registers for all the multiplier inputs must be enabled and use the same clock enable settings.

  • Page 64: Internal Coefficient And Pre-Adder For Fixed-Point Arithmetic

    4.1.4. Input Cascade for Fixed-Point Arithmetic The input register bank in Intel Agilex variable precision DSP block supports input cascade feature. This feature provides the capability of cascading the input bus within a DSP block and to another DSP block.
  • Page 65 4. Intel Agilex Variable Precision DSP Blocks Design Considerations UG-20213 | 2019.04.02 input register must be enabled when top delay register is enabled. The clock enable for both registers must be the same. Similarly, the input register must be enabled when bottom delay register is enabled.
  • Page 66 4. Intel Agilex Variable Precision DSP Blocks Design Considerations UG-20213 | 2019.04.02 Figure 48. Input Cascade in Fixed-Point Arithmetic 27 x 27 Mode ENA[2..0] scanin[26..0] CLR[0] ay[26..0] az[25..0] ax[26..0] scanout[26..0] 4.1.4.1. Dynamic Scanin When input cascade is used, the source of top multiplier can be dynamically switched...

  • Page 67: Chainout Adder

    4.2.1. Configurations for Input, Pipeline, and Output Registers The configurations for the input, pipeline, and output registers are restricted due to the timing model in Intel Agilex devices. Therefore these registers only support certain configurations. You must enable all registers within the same register level but you can use different clock enables.
  • Page 68 4. Intel Agilex Variable Precision DSP Blocks Design Considerations UG-20213 | 2019.04.02 4.2.1.1. FP32 Operation Modes Supported Register Configurations Table 26. Supported Register Configurations For FP32 Multiplication Mode Latency Input Register Pipeline Register Output Register fp32_mult_a_clk fp32_mult_b_clk mult_pipeline_cl mult_2nd_pipelin output_clken...
  • Page 69 4. Intel Agilex Variable Precision DSP Blocks Design Considerations UG-20213 | 2019.04.02 Table 29. Supported Register Configurations For FP32 Multiplication with Accumulation Mode Latency Data Input Register Adder Adder Multiplie Multiplie Adder Input Output r 1st r 2nd Register Register...
  • Page 70 4. Intel Agilex Variable Precision DSP Blocks Design Considerations UG-20213 | 2019.04.02 4.2.1.2. FP16 Operation Mode Supported Register Configurations Table 32. Supported Register Configurations For Sum of Two FP16 Multiplication Mode Latency Data Input Multiplier 1st Multiplier 2nd Adder Input...
  • Page 71 4. Intel Agilex Variable Precision DSP Blocks Design Considerations UG-20213 | 2019.04.02 Table 34. Supported Register Configurations For Sum of Two FP16 Multiplication with Accumulation Mode Latency Data Input Adder Adder Multiplie Multiplie Adder Input Adder Output Register r 1st...

  • Page 72: Chainout Adder

    4. Intel Agilex Variable Precision DSP Blocks Design Considerations UG-20213 | 2019.04.02 Latency Data Input Register Adder 1st Adder Multiplier Multiplier Adder Adder Output Pipeline Input Pipeline Register Register Pipeline Pipeline Pipeline Register Register Register Register Register fp32_add fp16_mul fp32_add...

  • Page 73: Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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