Modifying Interrupt Priorities - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
INT_MASK1
The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can
be read from or written to as a byte register. PUSHA saves this register on the stack and POPA
restores it.
7
NMI EXTINT
Bit
Number
7:6 Setting a bit enables the corresponding interrupt.
4:0
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
NMI
EXTINT
RI
TI
SSIO1
SSIO0
CBF
5 Reserved; for compatibility with future devices, write zero to this bit.
Figure 5-6. Interrupt Mask 1 (INT_MASK1) Register
5.5.2

Modifying Interrupt Priorities

Your software can modify the default priorities of maskable interrupts by controlling the interrupt
mask registers (INT_MASK and INT_MASK1). For example, you can specify which interrupts,
if any, can interrupt an interrupt service routine. The following code shows one way to prevent
all interrupts, except EXTINT (priority 14), from interrupting an SIO receive interrupt service
routine (priority12).
5-14
— RI
Function
Nonmaskable Interrupt
EXTINT Pin
SIO Receive
SIO Transmit
SSIO 1 Transfer
SSIO 0 Transfer
Slave Port Command Buffer Full
Address:
Reset State:
TI SSIO1 SSIO0
Standard Vector
FF203EH
FF203CH
FF2038H
FF2036H
FF2034H
FF2032H
FF2030H
0013H
00H
0
CBF