Modifying Interrupt Priorities - Intel 8XC196MC User Manual

8XC196MC, MD, MH USER'S MANUAL
PI_MASK (Continued)
The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests
associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow
timer interrupt (OVRTM).
7
8XC196MC —
7
8XC196MD —
7
8XC196MH —
Bit Bit
Number Mnemonic
0 OVRTM1
Figure 5-9. Peripheral Interrupt Mask (PI_MASK) Register (Continued)
5.5.1

Modifying Interrupt Priorities

Your software can modify the default priorities of maskable interrupts by controlling the interrupt
mask registers (INT_MASK and INT_MASK1). For example, you can specify which interrupts,
if any, can interrupt an interrupt service routine. The following code shows one way to prevent
all interrupts, except EXTINT (priority 14), from interrupting an A/D conversion-complete inter-
rupt service routine (priority 01).
SERIAL_RI_ISR:
PUSHA
LDB INT_MASK1, #01000000B
EI
POPA
RET
CSEG AT 02002H
DCW AD_DONE_ISR
5-18
— — WG
COMP5 — WG
SP1 — SP0
Timer 1 Overflow/Underflow
Setting this bit enables the timer 1 overflow/underflow interrupt.
The timer 1 and timer 2 overflow/underflow interrupts are associated with
the overflow/underflow timer interrupt (OVRTM). Setting INT_MASK.0
enables OVRTM.
; Save PSW, INT_MASK, INT_MASK1, & WSR
; (this disables all interrupts)
; Enable EXTINT only
; Enable interrupt servicing
; Service the AD_DONE interrupt
; Restore PSW, INT_MASK, INT_MASK1, &
; WSR registers
; fill in interrupt table
END
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Address:
Reset State:
— OVRTM2
— OVRTM2
— OVRTM2
Function
1FBCH
AAH
0
— OVRTM1
0
— OVRTM1
0
— OVRTM1