Situations That Increase Interrupt Latency; Calculating Latency - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
5.4.1

Situations that Increase Interrupt Latency

If an interrupt request occurs while any of the following instructions are executing, the interrupt
will not be acknowledged until after the next instruction is executed:
•
the signed prefix opcode (FE) for the two-byte, signed multiply and divide instructions
•
any of these eight protected instructions: DI, EI, DPTS, EPTS, POPA, POPF, PUSHA,
PUSHF (see Appendix A for descriptions of these instructions)
•
any of the read-modify-write instructions: AND, ANDB, OR, ORB, XOR, XORB
Both the unimplemented opcode interrupt and the software trap interrupt prevent other interrupt
requests from being acknowledged until after the next instruction is executed.
Each PTS cycle within a PTS routine cannot be interrupted. A PTS cycle is the entire PTS re-
sponse to a single interrupt request. In block transfer mode, a PTS cycle consists of the transfer
of an entire block of bytes or words. This means a worst-case latency of 500 states if you assume
a block transfer of 32 words from one external memory location to another. See Table 5-4 on page
5-10 for PTS cycle execution times.
5.4.2

Calculating Latency

The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol-
lowing the current instruction. The following worst-case calculation assumes that the current in-
struction is not a protected instruction. To calculate latency, add the following terms:
•
Time for the current instruction to finish execution (4 state times).
— If this is a protected instruction, the instruction that follows it must also execute before
the interrupt can be acknowledged. Add the execution time of the instruction that
follows a protected instruction.
•
Time for the next instruction to execute. (The longest instruction, NORML, takes 39 state
times. However, the BMOV instruction could actually take longer if it is transferring a large
block of data. If your code contains routines that transfer large blocks of data, you may get a
more accurate worst-case value if you use the BMOV instruction in your calculation instead
of NORML. See Appendix A for instruction execution times.)
•
For standard interrupts only, the response time to get the vector and force the call
— in 64-Kbyte mode, 11 state times for an internal stack or 13 for an external stack
(assuming a zero-wait-state bus)
— in 1-Mbyte mode, 15 state times for an internal stack or 18 for an external stack
(assuming a zero-wait-state bus)
5-8