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Intel Agilex User Manual

Embedded memory
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UG-20208 | 2019.04.02
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Summary of Contents for Intel Agilex

  • Page 1 ® ™ Intel Agilex Embedded Memory User Guide Subscribe UG-20208 | 2019.04.02 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    3.4. Consider Power-Up State and Memory Initialization..........33 3.5. Reduce Power Consumption.................. 34 3.6. Advanced Settings in Intel Quartus Prime Software for Memory........34 4. Intel Agilex Embedded Memory Debugging..............35 5. Document Revision History for the Intel Agilex Embedded Memory User Guide.... 36 ® ™ Intel...

  • Page 3: Intel ® Agilex ™ Embedded Memory Overview

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 4 ® ™ 1. Intel Agilex Embedded Memory Overview UG-20208 | 2019.04.02 Table 1. Intel Agilex Embedded Memory Features This table summarizes the features supported by the Intel Agilex embedded memory blocks. Features eSRAM M20K MLAB Maximum operating 750 MHz •...
  • Page 5 Agilex Embedded Memory Overview UG-20208 | 2019.04.02 Features eSRAM M20K MLAB Error Correction Code (ECC) • Soft IP using the Intel • Soft IP using the Intel Soft IP using the Intel ® support Quartus Prime software Quartus Prime software Quartus Prime software •...

  • Page 6: Intel Agilex Embedded Memory Architecture And Features

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 7: Data Byte Output

    You can control the output value for the masked byte in the M20K blocks or MLABs in the same-port read-during-write mode by using the Platform Designer in Intel Quartus Prime software.

  • Page 8: Byte Enable Behavior

    FFFFEFFF FFFFFF12 ABCDEF12 ABFFFFFF 2.2. Address Clock Enable Support Intel Agilex embedded memory blocks support address clock enable. When you enable address clock enable ( = 1), it holds the previous address value. addressstall Note: 1. Only simple dual-port mode supports this feature.
  • Page 9 2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 2. Address Clock Enable This figure shows an address clock enable block diagram. address[0] address[0] address[0] register address[N] address[N] address[N] register addressstall clock Figure 3. Address Clock Enable During Read Cycle This figure shows the address clock enable behavior during read cycle.

  • Page 10: Asynchronous Clear And Synchronous Clear

    2.3. Asynchronous Clear and Synchronous Clear The Intel Agilex M20K and MLAB embedded memory blocks support asynchronous clear and synchronous clear on output latches and output registers. Note: The M20K blocks support asynchronous clear on read address registers, but is limited only to simple dual-port and simple quad-port modes.
  • Page 11 2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 5. Behavior of Asynchronous Clear and Synchronous Clear in Registered Mode Registered asynclr regdout RD1 RD2 stay cleared until cleared by asynclr when next read cycle asynclr signal asserts...

  • Page 12: Memory Blocks Error Correction Code Support

    2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 7. Behavior When Asynchronous Clear is Used on Read Address Register in Registered and Unregistered Modes Registered/Unregistered asynclr regdout Output is data at Output stays as address 0...

  • Page 13: Parity Bit

    2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 eSRAM Blocks For eSRAM blocks, ECC performs single-error correction and double-error detection in a 64-bit word. The eSRAM blocks have built-in support for ECC when in ×64-wide simple dual-port mode.

  • Page 14: Error Correction Code Truth Table

    The error has been corrected at the outputs. The corrected data appears at the outputs but the memory array is not updated. 2.5. Intel Agilex Embedded Memory Clocking Modes Each Intel Agilex embedded memory operation mode has supporting clocking modes. ® ™ Intel Agilex...

  • Page 15: Single Clock Mode

    2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Table 8. Memory Blocks Clocking Modes Supported for Each Memory Mode Clocking Mode Memory Mode Single-Port Simple True Dual-Port Simple Single-Port Dual-Port ROM Dual-Port Quad-Port Single clock mode Read/write...

  • Page 16: Output Read Data In Simultaneous Read/Write

    To save power, you can control the shutdown of a particular register using the clock enables. 2.6. Intel Agilex Embedded Memory Configurations Table 9. Supported Embedded Memory Block Configurations This table lists the maximum configurations supported for the Intel Agilex embedded memory blocks. Embedded Memory Block Depth (bits) Programmable Width MLAB ×16, ×18, or ×20...

  • Page 17: Force-To-Zero

    2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Operation Mode Mixed-width Ratio Without Byte Enable With Byte Enable Note: 8, 16, and 32 are emulated. For emulated ratio, use the .mif dimension of the larger width port.
  • Page 18 2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 9. Coherent Read Memory Behavior for Intel Agilex Blocks This figure shows an example of the coherent read memory behavior when the output is registered if the M20K blocks does not read when the clear signal is asserted high.
  • Page 19 2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 10. Simplified Block Diagram of Coherent Read Memory Circuitry M20K Block C! = N C && FWD2 Q output Memory C || N OutReg writeData wraddress_reg FWD2 wraddress...

  • Page 20: Forwarding Logic

    2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 12. Coherent Read Memory Behavior for Registered Output This figure shows the waveform of the coherent read memory when the output is registered. clk_enable rden wren aclr F287D...
  • Page 21 2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 13. Example Forwarding Logic with Simplified Coherent Read Memory Circuitry C! = N M20K Block C && FWD2 Q output C || N Memory OutReg writeData FWD2 wraddress_reg...

  • Page 22: Freeze Logic

    2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 15. Pipelining Waveform When Output of M20K Blocks is Registered This figure shows the waveform of the pipelining with the write enable ( ) signal is high. wren...
  • Page 23 2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 The TDP dual clock emulator consists of two DCFIFOs and a single RAM block. The DCFIFO handles clock domain crossing (CDC) issues for the control signals and is a temporary buffer for data storage before and after being processed by the RAM block.
  • Page 24 2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 17. Output Condition of Port B clock_a clock_b valid wren_a wren_b rden_a rden_b data_a data_b address_a address_b enable_a enable_b Notes: 1. Latency of 2 clock_b clock cycle. 2. Valid data output (q_b) at Port B.
  • Page 25 2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 Figure 18. Read-During-Write Condition of Port A clock_a clock_b valid wren_a wren_b rden_a rden_b data_a data_b address_a address_b enable_a enable_b Notes: 1. Write enable (wren_a) signal at Port A asserts.

  • Page 26: Initial Value Of Read And Write Address Registers

    2. Intel Agilex Embedded Memory Architecture and Features UG-20208 | 2019.04.02 2.11. Initial Value of Read and Write Address Registers In Intel Agilex devices, the M20K blocks does not have freeze register ( ) in frzreg hardware to clear the address registers after entering user mode. This results in a non-deterministic address value in hardware before you can send any valid address.

  • Page 27: Intel Agilex Embedded Memory Design Considerations

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 28: Customize Read-During-Write Behavior

    3. Intel Agilex Embedded Memory Design Considerations UG-20208 | 2019.04.02 3.3. Customize Read-During-Write Behavior Customize the read-during-write behavior of the memory blocks to suit your design requirements. Figure 21. Read-During-Write Data Flow This figure shows the difference between the two types of read-during-write operations available: same port and mixed port.

  • Page 29: Mixed-Port Read-During-Write Mode

    3. Intel Agilex Embedded Memory Design Considerations UG-20208 | 2019.04.02 Figure 22. Same-Port Read-During-Write: New Data Mode This figure shows sample functional waveforms of same-port read-during-write behavior in the New Data mode. clk_a address rden wren byteena data_a A123 B456...
  • Page 30 M20K, MLAB The RAM produces Don't Care or Unknown value. • For M20K, the Intel Quartus Prime software does not analyze the timing between write and read operations. • For MLAB, the Intel Quartus Prime software does not analyze the timing between write and read operations by default.
  • Page 31 3. Intel Agilex Embedded Memory Design Considerations UG-20208 | 2019.04.02 Figure 24. Mixed-Port Read-During-Write: New Data Mode This figure shows a sample functional waveform of mixed-port read-during-write behavior for the New Data mode. clk_a&b wren_a address_a data_a AAAA BBBB CCCC...
  • Page 32 3. Intel Agilex Embedded Memory Design Considerations UG-20208 | 2019.04.02 Figure 26. Mixed-Port Read-During-Write: Don't Care Mode This figure shows a sample functional waveform of mixed-port read-during-write behavior for the Don't Care mode. This behavior is only applicable for M20K blocks.

  • Page 33: Consider Power-Up State And Memory Initialization

    3. Intel Agilex Embedded Memory Design Considerations UG-20208 | 2019.04.02 Figure 27. Mixed-Port Read-During-Write: New_a_old_b Mode This figure shows a sample functional waveform of mixed-port read-during-write behavior for the New_a_old_b mode. clk_a&b address_a address2_a address_b address2_b wren_a wren_b rden_a rden_b...

  • Page 34: Reduce Power Consumption

    Zero (cleared) By default, the Intel Quartus Prime software initializes the embedded memory block in Intel Agilex devices to zero, unless you specify in the memory contents in a .mif The MLAB and M20K embedded memory blocks support initialization with a .mif...

  • Page 35: Intel Agilex Embedded Memory Debugging

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 36: Document Revision History For The Intel Agilex Embedded Memory User Guide

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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