Spi Main Features - ST STM32F423 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
29.1.1

SPI main features

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Master or slave operation
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Full-duplex synchronous transfers on three lines
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Half-duplex synchronous transfer on two lines (with bidirectional data line)
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Simplex synchronous transfers on two lines (with unidirectional data line)
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8-bit to 16-bit transfer frame format selection
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Multimaster mode capability
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8 master mode baud rate prescalers up to f
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Slave mode frequency up to f
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NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
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Programmable clock polarity and phase
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Programmable data order with MSB-first or LSB-first shifting
•
Dedicated transmission and reception flags with interrupt capability
•
SPI bus busy status flag
•
SPI Motorola support
•
Hardware CRC feature for reliable communication:
–
–
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Master mode fault, overrun flags with interrupt capability
•
CRC Error flag
•
1-byte/word transmission and reception buffer with DMA capability: Tx and Rx requests
936/1324
CRC value can be transmitted as last byte in Tx mode
Automatic CRC error checking for last received byte
/2.
PCLK
/2.
PCLK
RM0430 Rev 8
RM0430