Table 9.3 Operation Of Channels 0 And 1 When Bit Ice Is Set To 1 In 8Tcsr1 Register; Table 9.4 Operation Of Channels 2 And 3 When Bit Ice Is Set To 1 In 8Tcsr3 Register - Hitachi H8/3062 Hardware Manual

Table 9.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register
Register
Register Function
TCORA0 Compare match
operation
TCORB0 Compare match
operation
TCORA1 Compare match
operation
TCORB1 Input capture
operation
Table 9.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register
Register
Register Function
TCORA2 Compare match
operation
TCORB2 Compare match
operation
TCORA3 Compare match
operation
TCORB3 Input capture
operation
Status Flag Change
CMFA changed from 0
to 1 in 8TCSR0 by
compare match
CMFB not changed
from 0 to 1 in 8TCSR0
by compare match
CMFA changed from 0
to 1 in 8TCSR1 by
compare match
CMFB changed from 0
to 1 in 8TCSR1 by
input capture
Status Flag Change
CMFA changed from 0
to 1 in 8TCSR2 by
compare match
CMFB not changed
from 0 to 1 in 8TCSR2
by compare match
CMFA changed from 0
to 1 in 8TCSR3 by
compare match
CMFB changed from 0
to 1 in 8TCSR3 by
input capture
Timer Output
Capture Input Interrupt Request
TMO output CMIA0 interrupt request
0
controllable generated by compare
match
No output from CMIB0 interrupt request
TMO not generated by compare
0
match
TMIO is dedicated CMIA1 interrupt request
1
input capture pin generated by compare
match
TMIO is dedicated CMIB1 interrupt request
1
input capture pin generated by input
capture
Timer Output
Capture Input Interrupt Request
TMO output CMIA2 interrupt request
2
controllable generated by compare
match
No output from CMIB2 interrupt request
TMO not generated by compare
2
match
TMIO is dedicated CMIA3 interrupt request
3
input capture pin generated by compare
match
TMIO is dedicated CMIB3 interrupt request
3
input capture pin generated by input
capture
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