Bus Timing - Hitachi H8/3006 Hardware Manual

20.3.3

Bus Timing

Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 20.8 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 20.9 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 20.10 shows the timing of the external three-state access cycle with one wait state
inserted.
• Burst ROM access timing: burst cycle two-state
Figure 20.11 shows the timing of the burst cycle two-state access.
• Burst ROM access timing: burst cycle three-state
Figure 20.12 shows the timing of the burst cycle three-state access.
• Bus-release mode timing
Figure 20.13 shows the bus-release mode timing.
596