Cpu Interface; 16-Bit Accessible Registers - Hitachi H8/3035 Series Hardware Manual

Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt requested by the IMFA flag in TSR when IMFA is set to 1.
Bit 0
IMIEA Description
0 IMIA interrupt requested by IMFA is disabled
1 IMIA interrupt requested by IMFA is enabled

8.3 CPU Interface

8.3.1 16-Bit Accessible Registers

The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers
A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit
data bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 8-6 and 8-7 show examples of word access to a timer counter (TCNT). Figures 8-8, 8-9,
8-10, and 8-11 show examples of byte access to TCNTH and TCNTL.
Internal data bus
H
CPU L
Figure 8-6 Access to Timer Counter (CPU Writes to TCNT, Word)
Internal data bus
H
CPU L
Figure 8-7 Access to Timer Counter (CPU Reads TCNT, Word)
Bus interface
Bus interface
H
L
TCNTH TCNTL
H
L
TCNTH TCNTL
(Initial value)
Module
data bus
Module
data bus
195