A/D Conversion Timing; A/D Conversion Time (Single Mode) - Hitachi H8/500 Series Hardware Manual

ø
Internal address
bus
Write signal
Input sampling
timing
ADF
(1)
(2)
t
D
t
SPL
t
CONV
Table 15-4 A/D Conversion Time (Single Mode)
Item
Synchronization delay
Input sampling time
Total A/D conversion time
Note: Values in the table are numbers of states.
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(1)
(2)
t t
D SPL
: ADCSR write cycle
: ADCSR address
: Synchronization delay
: Input sampling time
: Total A/D conversion time
Figure 15-5 A/D Conversion Timing
Symbol
t
D
t
SPL
t
CONV
t
CONV
CKS = "0"
Min Typ Max
18 — 33
— 63 —
259 — 274
288
CKS = "1"
Min Typ Max
10 — 17
— 31 —
131 — 138