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Bit 1: CKE1
Bit 0: CKE0
0
0
1
1
0
1
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
14.2.7
Serial Status Register (SSR)
Bit
7
TDRE
Initial value
1
Read/Write
R/(W)*
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, subactive, or subsleep mode.
256
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
6
5
RDRF
OER
0
0
R/(W)*
R/(W)*
Description
Clock Source
Internal clock
Internal clock
Internal clock
Reserved
External clock
External clock
Reserved
Reserved
4
3
FER
PER
0
0
R/(W)*
R/(W)*
SCK
Pin Function
3
I/O port
1
*
Serial clock output
Clock output
Clock input
*
Serial clock input
2
1
TEND
MPBR
1
0
R
R
1
*
2
*
3
0
MPBT
0
R/W
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