Dtc Transfer Count Register B (Crb); Dtc Enable Registers (Dtcer) - Hitachi H8S/2628 Hardware Manual

8.2.6

DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
8.2.7

DTC Enable Registers (DTCER)

DTCER is comprised of seven registers; DTCERA to DTCERG, and is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.1. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit Bit Name Initial Value
7 DTCE7 0
6 DTCE6 0
5 DTCE5 0
4 DTCE4 0
3 DTCE3 0
2 DTCE2 0
1 DTCE1 0
0 DTCE0 0
Rev. 1.0, 09/02, page 102 of 568
R/W Description
R/W DTC Activation Enable
R/W
Setting this bit to 1 specifies a relevant interrupt
R/W
source as a DTC activation source.
R/W
[Clearing conditions]
R/W
R/W
• When the DISEL bit in MRB is 1 and the data
R/W
transfer has ended
R/W
• When the specified number of transfers have
ended
These bits are not cleared when the DISEL bit is 0
and the specified number of transfers have not been
completed.