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7.2.2
I/O Address Registers (IOAR)
An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or
destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits
are all 1 (H'FFFF).
Bit
Initial value
Read/Write
R/W
An IOAR functions as a source or destination address register depending on how the DMAC is
activated: as a source address register if activation is by a receive-data-full interrupt from the SCI
(channel 0) or by a conversion-end interrupt from the A/D converter, and as a destination address
register otherwise.
The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed.
The IOARs are not initialized by a reset or in standby mode.
7.2.3
Execute Transfer Count Registers (ETCR)
An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the
number of transfers to be executed. These registers function in one way in I/O mode and idle
mode, and another way in repeat mode.
• I/O mode and idle mode
Bit
15
Initial value
Read/Write
R/W
In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by
1 each time one transfer is executed. The transfer ends when the count reaches H'0000.
7
6
5
R/W
R/W
Source or destination address
14
13
12
11
R/W
R/W
R/W
R/W
4
3
Undetermined
R/W
R/W
10
9
8
7
Undetermined
R/W
R/W
R/W
R/W
R/W
Transfer counter
2
1
R/W
R/W
6
5
4
3
2
R/W
R/W
R/W
R/W
0
R/W
1
0
R/W
R/W
189
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