Figure 6.6 Example Of Consecutive External Space Accesses In Address Update Mode 2 - Hitachi H8/3062 Hardware Manual

basically no problem if the H8/3062F-ZTAT is replaced with the H8/3062F-ZTAT R-mask
version, H8/3062 mask ROM version, H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT
B-mask version, H8/3064 mask ROM B-mask version, or H8/3062 mask ROM B-mask version.
However, the following points should be noted.
• ADRCR is allocated to address H'FEE01E. In the H8/3062F-ZTAT, the corresponding
address is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E
in the program.
• When address update mode 2 is selected, the address in an internal space (on-chip memory or
internal I/O) access cycle is not output externally.
• In order to secure address holding with respect to the rise of RD, when address update mode 2
is used an external space read access must be completed within a single access cycle. For
example, in a word access to 8-bit access space, the bus cycle is split into two as shown in
figure 6.6., and so there is not a single access cycle. In this case, address holding is not
guaranteed at the rise of RD between the first (even address) and second (odd address) access
cycles (area inside the ellipse in the figure).
Address update
mode 2
RD

Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2

144
On-chip
(8-bit space word access)
memory cycle
Even address
External read cycle
Odd address
On-chip
memory cycle