Resets; Table 3.5-1 Reset Source - Fujitsu F2MC-8L Series Hardware Manual

3.5

Resets

The MB89120/120A series supports the following four types of reset source:
• External reset
• Software reset
• Watchdog reset
• Power-on reset (optional)
Generation of the main clock oscillation stabilization delay time depends on the
operation mode or option setting.
Reset Source

Table 3.5-1 Reset Source

Reset source
External reset
Software reset
Watchdog reset
Power-on reset
External reset
Inputting an "L" level to the external reset pin (RST) generates an external reset. Returning the
reset pin to the "H" level wakes up the CPU from the external reset.
The external reset pin can also function as a reset output pin (optional).
Software reset
Writing "0" to the software reset bit in the standby control register (STBC: RST) generates a
four-instruction cycle reset.
Watchdog reset
The watchdog reset generates a four-instruction cycle reset if data is not written to the watchdog
timer control register (WDTC) within a fixed time after the watchdog timer starts.
Power-on reset
Products can be set to with or without power-on reset (optional).
On products with power-on reset, turning on the power generates a reset.
On products without power-on reset, an external reset circuit is required to generate a reset
when the power is turned on.
Reset Sources and Main Clock Oscillation Stabilization Delay Time
The oscillation stabilization delay time taken after a reset depends on the operation mode in
which the reset occurs and on the power-on reset option setting.
Set the external reset pin to the "L" level.
Write "0" to the software reset bit in the standby control register (STBC: RST).
Watchdog timer overflow
Power is turned on (only on products with a power-on reset).
Reset conditions
3.5 Resets
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