Interrupt Level Setting Registers (Ilr1, Ilr2, Ilr3); Figure 3.4-1 Structure Of Interrupt Level Setting Registers; Table 3.4-2 Interrupt Level Setting Bit And Interrupt Level - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
3.4.1

Interrupt Level Setting Registers (ILR1, ILR2, ILR3)

The interrupt level setting registers (ILR1, ILR2, ILR3) together contain 12 blocks of 2-
bit data, with each data corresponding to an interrupt request from a peripheral
function. The interrupt level for each interrupt is set in that interrupt's corresponding
2-bit data (interrupt level setting bits).
Structure of Interrupt Level Setting Registers (ILR1, ILR2, ILR3)
Register Address
ILR1 007C
ILR2 007D
ILR3 007E
W: Write-only
Two bits of the interrupt level setting registers are allocated to each interrupt request. The value
of the interrupt level setting bits in these registers sets the interrupt priority (interrupt levels 1 to
3).
The interrupt level setting bits are compared with the interrupt level bits in the condition code
register (CCR: IL1, IL0).
The CPU does not accept interrupt requests set to interrupt level 3.
Table 3.4-2 shows the relationship between the interrupt level setting bits and the interrupt
levels.

Table 3.4-2 Interrupt Level Setting Bit and Interrupt Level

L01 to LB1
Tip:
The interrupt level bits in the condition code register (CCR: IL1, IL0) are normally "11" during
main program execution.
42

Figure 3.4-1 Structure of Interrupt Level Setting Registers

Bit 7 Bit 6 Bit 5
L31 L30 L21
H
W W W
L71 L70 L61
H
W W W
LB1 LB0 LA1
H
W W W
L00 to LB0
0 0
0 1
1 0
1 1
Bit 4 Bit 3 Bit 2
L20 L11 L10
W W W
L60 L51 L50
W W W
LA0 L91 L90
W W W
Request interrupt
level
1
2
3
Bit 1 Bit 0 Initial value
L01 L00 11111111
W W
L41 L40 11111111
W W
L81 L80 11111111
W W
High-low
High
Low (no interrupt)
B
B
B