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3.8.1
Interrupt Level
Interrupt levels are 0 to 31; they are managed with five bits.
■ Interrupt Levels
Each interrupt level is assigned as follows.
Table 3.8-1 Interrupt Levels
Level
Binary
Decimal
00000
0
B
...
...
...
...
00011
3
B
00100
4
B
00101
5
B
...
...
...
...
01110
14
B
01111
15
B
10000
16
B
10001
17
B
...
...
...
...
11110
30
B
11111
31
B
Interrupt levels 16 to 31 can be operated.
Interrupt levels have no effect on the undefined instruction exception, coprocessor absence trap,
coprocessor error trap, or INT instruction. Neither they change the ILM value.
Interrupt source
(System-reserved)
...
...
(System-reserved)
{
INTE instruction
Step trace trap
(System-reserved)
...
...
(System-reserved)
NMI (for user)
Interrupt
Interrupt
...
...
Interrupt
–
CHAPTER 3 CPU AND CONTROL UNITS
Note
When the original ILM value is 16 to 31, the
ILM register cannot be set to a value in that
range by a program.
No user interrupt is allowed with the ILM
register set.
No interrupt is allowed with the ICR set.
49
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