Condition Code Register (Ccr); Figure 3.2-2 Structure Of Condition Code Register - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
3.2.1

Condition Code Register (CCR)

The condition code register (CCR) located in the lower 8 bits of the program status
(PS) consists of the C, V, Z, N, and H bits indicating the results of arithmetic operations
and the contents of transfer data, and the I, IL1, and IL0 bits for control whether or not
the CPU accepts interrupt requests.
Structure of Condition Code Register (CCR)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R4 R3
PS
X: Indeterminate
Arithmetic Operation Result Bits
Half-carry flag (H)
Set to "1" when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an
arithmetic operation. Cleared to "0" otherwise. As this flag is for the decimal adjustment
instructions, do not use this flag in cases other than addition or subtraction.
Negative flag (N)
Set to "1" if the most significant bit (MSB) is set to "1" as a result of an arithmetic operation.
Cleared to "0" when the bit is set to "0".
Zero flag (Z)
Set to "1" when an arithmetic operation results in "0". Cleared to "0" otherwise.
Overflow flag (V)
Set to "1" if the complement on 2 overflows as a result of an arithmetic operation. Cleared to "0"
if the overflow does not occur.
Carry flag (C)
Set to "1" when a carry from bit 7 or borrow to bit 7 occurs as a result of an arithmetic operation.
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Figure 3.2-2 Structure of Condition Code Register

RP
R2 R1 R0 — —
Half-carry flag
Interrupt enable flag
Interrupt level bits
Negative flag
Zero flag
Overflow flag
Carry flag
CCR
— H I IL1 IL0
CCR initial value
N Z V C
X011XXXX
B