Figure 3.2.1A Structure Of Condition Code Register; Figure 3.2.1B Change Of Carry Flag By Shift Instruction - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.2 Dedicated Registers
3.2.1 Condition Code Register (CCR)
The condition code register (CCR) located in the lower 8 bits of the program status
(PS) consists of the C, V, Z, N, and H bits indicating the results of arithmetic
operations and the contents of transfer data, and the I, IL1, and IL0 bits for control
whether or not the CPU accepts interrupt requests.
n Structure of Condition Code Register (CCR)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PS
X: Indeterminate
n Arithmetic Operation Result Bits
Half-carry flag (H)
l
Set when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an
arithmetic operation. Cleared otherwise. As this flag is for the decimal adjustment instructions,
do not use this flag in cases other than addition or subtraction.
l Negative flag (N)
Set if the most significant bit (MSB) is set to 1 as a result of an arithmetic operation. Cleared
when the bit is set to 0.
l Zero flag (Z)
Set when an arithmetic operation results in 0. Cleared otherwise.
Overflow flag (V)
l
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow
does not occur.
Carry flag (C)
l
Set when a carry from bit 7 or borrow to bit 7 occurs as a result of an arithmetic operation. Cleared
otherwise. Set to the shift-out value in case of a shift instruction.
Figure 3.2.1b shows the change of the carry flag by a shift instruction.
• Left shift (ROLC)
38
CHAPTER 3 CPU
RP
R4 R3 R2 R1 R0 —
Half-carry flag
Interrupt enable flag
Interrupt level bits
Negative flag
Zero flag
Overflow flag
Carry flag

Figure 3.2.1a Structure of Condition Code Register

Bit 7
C

Figure 3.2.1b Change of Carry Flag by Shift Instruction

— — H I IL1 IL0
• Right shift (RORC)
Bit 7
Bit 0
CCR
CCR initial value
N Z V C
X011XXXX
Bit 0
B
C
MB89620 series