Condition Code Register (Ccr); System Condition Code Register (Scr); Table 2-5: Condition Code Register; Table 2-6: System Condition Code Register - Fujitsu F2MC-FR Series Application Note

2.5.1.2 Condition Code Register (CCR)

The CCR consists of the following bits:
Bit Bit Initial
No. Name Value
7
- -
6 SV -
5 S 0
4 I 0
3 N X
2 Z x
1
V x
0 C x
Interrupts can be enabled globally by the C language extension __EI() and disabled by
__DI().
There is no direct bit access to the CCR in assembler, but bits can be set indirectly with
logical instructions: Setting the I-Bit: ORCCR #10 and clearing it: ANDCCR #EF.
Please note, that __DI() and __EI() cannot be set consecutively. Please set at least one
instruction in-between, such as a NOP.
Wrong
__DI();
__EI();
__EI();
__DI();

2.5.1.3 System Condition Code Register (SCR)

The SCR consists of the following bits:
Bit Bit Initial
No. Name Value
10 D1 x
9 D0 x
8 T 0
MCU-AN-300055-E-V10
INTERRUPTS
Chapter 2 Interrupt Types
Description
-
Supervisor Mode Flag.
1 = User Mode, 0 = Supervisor Mode
System/User Stack Flag. 0 = System Stack, 1 = User Stack.
This bit is set to "1" after in case of all EITs
Global Interrupt Enable Flag
Negative Flag
Zero Flag
Overflow Flag
Carry Flag

Table 2-5: Condition Code Register

__DI();
__wait_nop;
__EI();
__EI();
__wait_nop();
__DI();
Description
Step Division Flag.
These bits hold intermediate data during the execution of step
division.
Step Trace Trap Flag.
Setting this bit enables step trace trap. Its used by the emulator.

Table 2-6: System Condition Code Register

- 12 -
Correct
© Fujitsu Microelectronics Europe GmbH