Appendix; Comparison Between Debugging With External Sram And Internal Flash Memory; Source Code Of The Procedure Files; Cs0_Adr_000000H.prc - Fujitsu FR Series Application Note
32-bit microcontroller
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Also See for FR Series:
- Application note (29 pages) ,
- Instruction manual (314 pages) ,
- Instruction manual (304 pages)
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5 Appendix
5.1 Comparison between debugging with external SRAM and internal FLASH
memory
code located at
characteristic
loading the application
hardware
preparations
runtime-performance
debugging feature
5.2 Source Code of the procedure files
5.2.1 CS0_ADR_000000h.PRC
# THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU
# MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
# ELIGIBILITY FOR ANY PURPOSES.
#
# CS0_ADR_000000h.PRC
# ===========
#
# Procedurefile for the FR-Emulator - Target : MB91FV360.
# Should be executed before loading any target-file into
# the emulator.
# The file sets the PLL-Clock to 32MHz for faster download
# and enables ONLY CS0 for the ROM-area 00:0000...0F:FFFF.
# Setting the CS0-Jumper to SRAM on the emulation board
# allows to emulate ROM-areas the same way as in the Flash-Chip.
# MB2197-120 : S1-0 : EVA;
#
# V1.0 by JR
# last modification : 23.10.2001
#
printf "\nprocedure file : CS0_ADR_000000h.prc\n\n"
printf "set CS0 : 00:0000 .. 0F:FFFF\n"
disable verifymode
set memory/halfword H'640=H'00
© Fujitsu Microelectronics Europe GmbH
Chapter 5 Appendix
SRAM
code is loaded via
debugger menu
"Debug->Load target"
chip select needs to be
routed to SRAM
lower performance
no restrictions
Table 5 Summary
(C) Fujitsu Microelectronics Europe GmbH
S2-0 : SRAM
# because ASR/AMR are Write only
internal flash
code is programmed to
flash memory, last
longer then loading
the code to SRAM
chip select needs to be
routed to SRAM only
for programming
realistic target
performance
no software
breakpoints available
# ASR0=00 CS0-Begin=00:0000
- 23 -
AN-910011-18
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