Communication Prescaler Control Register (Sdcr) - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
17.2.3

Communication Prescaler Control Register (SDCR)

The configuration and functions of communication prescaler control register (SDCR)
are described.
■ Communication Prescaler Control Register (SDCR)
Figure 17.2-4 shows the bit configuration of communication prescaler control register (SDCR).
Figure 17.2-4 Communication Prescaler Control Register (SDCR)
SDCR bit
: 00005B
Address
R/W : Readable/Writable
: Undefined
X : Undefined value
The functions of each bit of the communication prescaler control register (SDCR) are described below.
[bit15] MD: Machine clock divide moDe select
Bit to enable the operation of the communication prescaler
MD
0
1
[bit11 to bit8] DIV3 to DIV0:DIVide3 to DIVide0
These bits determine the machine clock division ratio.
CM44-10137-6E
15 13
14
MD
H
(R/W)
DIV3 to DIV0
0000
B
0001
B
0010
B
0011
B
0100
B
0101
B
0110
B
0111
B
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 17 EXTENDED I/O SERIAL INTERFACE
17.2 Register in Extended I/O Serial Interface
12 11 10 9
DIV3 DIV2 DIV1
(R/W) (R/W) (R/W) (R/W)
Operation
Communication Prescaler stops.
Communication Prescaler is operating.
1-frequency division
2-frequency division
3-frequency division
4-frequency division
5-frequency division
6-frequency division
7-frequency division
8-frequency division
8
Communication prescaler
DIV0
control register
Initial value
Rate of division
0XXX0000
B
375