Communication Prescaler Control Register (Sdcr) - Fujitsu F2MC-16LX Hardware Manual

20.2.3

Communication Prescaler Control Register (SDCR)

The configuration and functions of communication prescaler control register (SDCR)
are described.
Communication Prescaler Control Register (SDCR)
Figure 20.2-4 shows the bit configuration of communication prescaler control register (SDCR).
Figure 20.2-4 Communication Prescaler Control Register (SDCR)
SDCR
: 00005B
Address
R/W : Readable/Writable
: Undefined
The functions of each bit of the communication prescaler control register (SDCR) are described below.
[bit 15] MD: Machine clock divide moDe select
Bit to enable the operation of the communication prescaler
MD
0
1
[bit 11 to bit 8] DIV3,DIV2,DIV1,DIV0:DIVide3 to DIVide0
These bits determine the machine clock division ratio.
DIV3 to DIV0
0000
0001
0010
0011
0100
0101
0110
0111
Note:
In the case of making changes to the rate of division, allow for two divisions of intervals as the
duration of stabilization of the clock before communication.
13
15 14
MD
H
(R/W)
Communication Prescaler stops.
Communication Prescaler is operating.
Rate of division
1-frequency division
B
2-frequency division
B
3-frequency division
B
4-frequency division
B
5-frequency division
B
6-frequency division
B
7-frequency division
B
8-frequency division
B
CHAPTER 20 EXTENDED I/O SERIAL INTERFACE
12 11 10
9
DIV0
DIV3 DIV2 DIV1
(R/W) (R/W) (R/W) (R/W)
Operation
8
Communication prescaler
control register
Initial value 0XXX0000
B
467