Communication Prescaler Control Register (Cdcr) - Fujitsu MB91150 Series Hardware Manual

CHAPTER 15 UART

15.4.5 Communication prescaler control register (CDCR)

The communication prescaler control register (CDCR) controls division of the machine
clock.
I Communication prescaler control register (CDCR)
The UART operation clock is obtained by dividing the machine clock. This communication
prescaler is designed to obtain a fixed baud rate for machine cycles. The configuration of the
communication prescaler control register (CDCR) is shown below.
Address
ch0:0000_004Eh
ch1:0000_004Ch
ch2:0000_0052h
ch3:0000_0050h
R/W: Read/write enabled
[Bit 15] MD (Machine clock device mode select)
This is the communication prescaler operation enable bit.
0: The communication prescaler stops.
1: The communication prescaler operates.
[Bits 11, 10, 9, 8] DIV3-0 (DIVide 3-0)
The machine clock division ratio is determined in accordance with Table 15.4-1
"Communication prescaler".
Table 15.4-1 Communication prescaler
MD
0
1
1
1
1
1
1
1
1
1
1
320
bit15 bit14 bit13 bit12
MD
R/W
DIV3 DIV2
-
0
0
0
0
0
0
0
0
1
1
bit11 bit10 bit9
DIV3 DIV2 DIV1
R/W R/W R/W
DIV1
- -
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
bit8
DIV0
R/W
Initial value 0---0000
B
DIV0 div
- Stop
0 1
1 2
0 3
1 4
0 5
1 6
0 7
1 8
0 9
1 10