Determining Event Status - Intel 8XC196NT User Manual

EPA_MASK
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with
the multiplexed EPA x interrupt
15
EPA4 EPA5
7
OVR2 OVR3
Bit
Number
15:10 Setting this bit enables the corresponding interrupt as a multiplexed EPA x interrupt
source.The multiplexed EPA x interrupt is enabled by setting its interrupt enable bit in the
interrupt mask register (INT_MASK.0 = 1).
Figure 10-12. EPA Interrupt Mask (EPA_MASK) Register
EPA_MASK1
The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated
with the multiplexed EPA x interrupt.
7
— —
Bit
Number
7:4 Reserved; for compatibility with future devices, write zeros to these bits.
3:0 Setting a bit enables the corresponding interrupt as a multiplexed EPA x interrupt source.
The multiplexed EPA x interrupt is enabled by setting its interrupt enable bit in the
interrupt mask register (INT_MASK.0 = 1).
Figure 10-13. EPA Interrupt Mask 1 (EPA_MASK1) Register

10.7 DETERMINING EVENT STATUS

In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event
(even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt
pending bit is set each time a programmed event is captured and the event time moves from the
capture buffer to the EPAx_TIME register. If the capture buffer is full when an event occurs, an
overrun interrupt pending bit is set.
EPA6 EPA7
OVR4 OVR5
Function
— —
Function
EVENT PROCESSOR ARRAY (EPA)
Reset State:
EPA8 EPA9
OVR6 OVR7
Reset State:
COMP0 COMP1 OVRTM1
Address: 1FA0H
0000H
8
OVR0 OVR1
0
OVR8 OVR9
Address: 1FA4H
00H
0
OVRTM2
10-27