Transceivers Interfaces And Communication Ports - Intel Cyclone 10 GX FPGA User Manual

4 Development Board Components
UG-20105 | 2017.12.18

4.9 Transceivers Interfaces and Communication Ports

4.9.1 Transceiver Channels
The Intel Cyclone 10 GX FPGA device has 12 channels of transceivers that work at
12.5 Gbps. The transceivers are organized in two banks, each bank has six channels.
Table 15. Transceiver Channel Allocation
Channel Number (Bank
1C)
0
1
2
3
4
5
4.9.2 PCIe Interface
The PCIe x4 Gen2 Hard IP with CvP is implemented in this development kit. The
position of the PCIe channels is fixed by the hard IP. This development kit is a PCIe
add-in card. The PCIe interface is configured to End-Point.
The PCIe interface has the following signals:
• Transceivers, x4, up to 5 Gbps
•
PCIE_REFCLKp/n
•
PCIE_SMBUS
•
PCIE_PERSTn
•
PCIE_WAKEn
The PCIe width can be selected with Jumper resistors:
• R506 installed, x1 mode
• R507 installed, x4 mode, this is the default mode
There are three power rails from PCIe golden finger connector:
• +12 V, +/- 8 %, up to 75 W, is used as power of the board
• +3.3 V, +/- 9 %, up to 10 W, is not used on this board
• +3.3 Vaux, +/- 9 %, 375 mA max, is not used since wakeup is not supported
4.9.3 SFP+ Interface
Two SFP+ connectors (J5, J6) are provided on the PCIe bracket. Each connector
supports a 10 GE SFP+ hot pluggable module.
Function (Bank 1C)
FMC_DP [0]
FMC_DP [1]
FMC_DP [2]
FMC_DP [3]
PCIe [0]
PCIe [1]
, 100 MHz from PCIe system
, 3.3V level-translated to 1.8V with U18
, 3.3V level-translated to 1.8V with U17
, 3.3V level-translated to 1.8V with U17, reserved
Channel Number (Bank
1D)
0
1
2
3
4
5
® ®
Intel Cyclone 10 GX FPGA Development Kit User Guide
Function (Bank 1D)
PCIe [2]
PCIe [3]
FMC_DP [4]
SFP+ 1
SFP+ 0
USB3.1
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