Sysctrl Register - Texas Instruments CC3200 Technical Reference Manual

Register Map
3.3.1.15 SYSCTRL Register (offset = D10h) [reset = 0h]
SYSCTRL is shown in
NOTE: his register can only be accessed from privileged mode. The SYSCTRL register controls features
of entry to and exit from low-power state.
31 30
23 22
15 14
7 6
RESERVED
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit Field
31-5 RESERVED
4 SEVONPEND
3 RESERVED
2 SLEEPDEEP
1 SLEEPEXIT
0 RESERVED
82
Cortex-M4 Peripherals
Figure 3-15 and described in
Figure 3-15. SYSCTRL Register
29 28
RESERVED
21 20
RESERVED
13 12
RESERVED
5 4
SEVONPEND
R/W-0h
Table 3-18. SYSCTRL Register Field Descriptions
Type Reset
R 0h
R/W 0h
R 0h
R/W 0h
R/W 0h
R 0h
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Table 3-18.
27 26
R-0h
19 18
R-0h
11 10
R-0h
3 2
RESERVED SLEEPDEEP
R-0h R/W-0h
Description
Wake Up on Pending
0h = Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
1h = Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
Deep Sleep Enable
0h = Use Sleep mode as the low power mode.
1h = Use Deep-sleep mode as the low power mode.
Sleep on ISR Exit Setting this bit enables an interrupt-driven
application to avoid returning to an empty main application.
0h = When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
1h = When returning from Handler mode to Thread mode, enter
sleep or deep sleep on return from an ISR.
SWRU367D – June 2014 – Revised May 2018
www.ti.com
25 24
17 16
9 8
1 0
SLEEPEXIT RESERVED
R/W-0h R-0h
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