Fmpi2C Master Mode - ST STM32F412 Reference Manual

RM0402
23.4.9

FMPI2C master mode

FMPI2C master initialization
Before enabling the peripheral, the FMPI2C master clock must be configured by setting the
SCLH and SCLL bits in the FMPI2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
A clock synchronization mechanism is implemented in order to support multi-master
environment and slave clock stretching.
In order to allow clock synchronization:
•
The low level of the clock is counted using the SCLL counter, starting from the SCL low
level internal detection.
•
The high level of the clock is counted using the SCLH counter, starting from the SCL
high level internal detection.
The FMPI2C detects its own SCL low level after a
edge, SCL input noise filters (analog + digital) and SCL synchronization to the I2CxCLK
clock. The FMPI2C releases SCL to high level once the SCLL counter reaches the value
programmed in the SCLL[7:0] bits in the FMPI2C_TIMINGR register.
The FMPI2C detects its own SCL high level after a
edge, SCL input noise filters (analog + digital) and SCL synchronization to I2CxCLK clock.
The FMPI2C ties SCL to low level once the SCLH counter is reached reaches the value
programmed in the SCLH[7:0] bits in the FMPI2C_TIMINGR register.
Consequently the master clock period is:
t t
SCL = SYNC1
The duration of t
–
–
–
–
The duration of t
–
–
–
–
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
+ t {[(SCLH+1) + (SCLL+1)] x (PRESC+1) x t
SYNC2 +
depends on these parameters:
SYNC1
SCL falling slope
When enabled, input delay induced by the analog filter.
When enabled, input delay induced by the digital filter: DNF
Delay due to SCL synchronization with FMPI2CCLK clock (2 to 3 FMPI2CCLK
periods)
depends on these parameters:
SYNC2
SCL rising slope
When enabled, input delay induced by the analog filter.
When enabled, input delay induced by the digital filter: DNF
Delay due to SCL synchronization with FMPI2CCLK clock (2 to 3 FMPI2CCLK
periods)
t
SYNC1
t
SYNC2
RM0402 Rev 6
delay depending on the SCL falling
delay depending on the SCL rising
}
I2CCLK
x t
I2CCLK
x t
I2CCLK
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