Figure 8. Generation Of Clock For Sai Master Mode (In Case Mclk Is Needed) - ST STM32L1 Series Application Note

Peripheral migration
When the clock is derived from one of the three internal PLLs, the three PLL inputs are
either HSI16, HSE or MSI (between 4 and 8 MHz) divided by a programmable factor PLLM
(from 1 to 8). This input is then multiplied by PLLN (from 8 to 86) to reach PLL VCO
frequency (should be between 64 and 344 MHz). It is finally divided by PLLP (7 or 17 on
Cat. 2 devices, [2...31] on Cat. 4 devices) to provide the input clock for SAI (max. 80 MHz)
When the Master clock MCLK is used by the external slave audio peripheral, the PLL output
is divided by SAI internal master clock divider factor (1, 2, 4, 6, 8, 10..., 30) to provide the
master clock (MCLK). The data bit clock is then derived from MCLK following the formula:
where (FRL + 1) = 8, 16, 32, 64, 128, 256:
• FRL is the number of bit clock cycles -1 in the audio frame.
•
(FRL + 1) should be a power of 2 higher or equal to 8.
SCK can also be directly connected to input clock of SAI when MCLK output is not needed.
The frame synchronization (FS) frequency is always MCLK / 256.

Figure 8. Generation of clock for SAI master mode (in case MCLK is needed)

Please refer to reference manuals for more details.
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SCK MCLK × ( FRL
=
DocID027094 Rev 3
1 ) ⁄ 256
+
AN4612