Flash Cpu2 Control Register (Flash_C2Cr) - ST STM32WL5 Series Reference Manual

Embedded Flash memory (FLASH)
Bit 5 PGAERR: programming alignment error
Bit 4 WRPERR: write protection error
Bit 3 PROGERR: programming error
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: operation error
Bit 0 EOP: end of operation
4.10.18

FLASH CPU2 control register (FLASH_C2CR)

Address offset: 0x064
Reset value: 0xC000 0000
Access: no wait state when no Flash memory operation is ongoing. Word, half-word and
byte access.
This register cannot be modified when CFGBSY is set in FLASH_C2SR.
•
When PESD is cleared in FLASH_C2SR, the register write access is stalled until
CFGBSY is cleared (for example by the other CPU).
•
When PESD is set in FLASH_C2SR, the register write access causes a bus error.
•
When PESD is set in FLASH_C2SR but there is no ongoing program or erase
operation, the register write access is completed. The requested program or erase
operation is suspended, BSY/CFGBSY is asserted and remains 1 until suspend is
deactivated. Consequently, PESD bit goes back to 0 and the suspended operation
completes.
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This bit is set by hardware when the data to program cannot be contained in the same
double-word (64-bit) Flash memory in case of standard programming, or if there is a change
of page during fast programming.
This bit is cleared by writing 1.
This bit is set by hardware when an address to be erased/programmed belongs to a write-
protected part (by WRP, PCROP or RDP Level 1) of the Flash memory.
This bit is cleared by writing 1.
This bit is set by hardware when a double-word address to be programmed contains a value
different from 0xFFFF FFFF FFFF FFFF before programming, except if the double-word
data to write is 0x0000 0000 0000 0000.
This bit is cleared by writing 1.
This bit is set by hardware when a Flash memory operation (program/erase) completes
unsuccessfully.
This bit is set only if error interrupts are enabled (ERRIE = 1) and cleared by writing 1.
This bit is set by hardware when one or more Flash memory operation (program/erase) has
been completed successfully.
This bit is set only if the end of operation interrupts are enabled (EOPIE = 1) and cleared by
writing 1.
RM0453 Rev 1
RM0453