Debug Mode; Table 109. Min/Max Iwdg Timeout Period At 32 Khz (Lsi); Figure 204. Independent Watchdog Block Diagram - ST STM32F412 Reference Manual

Independent watchdog (IWDG)
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
20.3.3

Debug mode

When the microcontroller enters debug mode (Cortex
counter either continues to work normally or stops, depending on DBG_IWDG_STOP
configuration bit in DBG module. For more details, refer to
APB1 freeze register
CORE
LSI
(40 kHz)
VDD voltage domain
Note: The watchdog function is implemented in the V
Stop and Standby modes.
Prescaler divider
/16
/32
/64
/128
/256
1. These timings are given for a 32 kHz clock but the microcontroller internal RC frequency can vary. Refers
to LSI oscillator characteristics table in device datasheet for from max and min values.
606/1163
(DBGMCU_APB1_FZ).

Figure 204. Independent watchdog block diagram

Prescaler register
Status register
IWDG_PR
IWDG_SR
8-bit
prescaler

Table 109. Min/max IWDG timeout period at 32 kHz (LSI)

PR[2:0] bits
/4 0
/8 1
2
3
4
5
6
®
Reload register
IWDG_RLR
12-bit reload value
12-bit downcounter
voltage domain that is still functional in
DD
Min timeout (ms) RL[11:0]=
0x000
0.125
0.25
0.5
1
2
4
8
RM0402 Rev 6
-M4 with FPU core halted), the IWDG
Section 30.16.4: Debug MCU
Key register
IWDG_KR
IWDG reset
(1)
Max timeout (ms) RL[11:0]=
0xFFF
512
1024
2048
4096
8192
16384
32768
RM0402
MS19944V2