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RM0402
9.5.3
DMA low interrupt flag clear register (DMA_LIFCR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
CTCIF3 CHTIF3 CTEIF3 CDMEIF3
15
14
13
12
Res.
Res.
Res.
Res.
CTCIF1 CHTIF1 CTEIF1 CDMEIF1
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: stream x clear transfer complete interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register.
Bits 26, 20, 10, 4 CHTIFx: stream x clear half transfer interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register.
Bits 24, 18, 8, 2 CDMEIFx: stream x clear direct mode error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register.
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: stream x clear FIFO error interrupt flag (x = 3 to 0)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register.
9.5.4
DMA high interrupt flag clear register (DMA_HIFCR)
Address offset: 0x00C
Reset value: 0x0000 0000
31
30
29
28
27
Res. Res. Res. Res.
CTCIF7 CHTIF7 CTEIF7 CDMEIF7
w
15
14
13
12
11
Res. Res. Res. Res.
CTCIF5 CHTIF5 CTEIF5 CDMEIF5
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: stream x clear transfer complete interrupt flag (x = 7 to 4)
Bits 26, 20, 10, 4 CHTIFx: stream x clear half transfer interrupt flag (x = 7 to 4)
Bits 25, 19, 9, 3 CTEIFx: stream x clear transfer error interrupt flag (x = 7 to 4)
27
26
25
w
w
w
11
10
9
w
w
w
26
25
24
w
w
w
10
9
8
w
w
w
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register.
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register.
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register.
Direct memory access controller (DMA)
24
23
22
21
Res.
CFEIF3 CTCIF2
w
w
w
8
7
6
5
Res.
CFEIF1 CTCIF0
w
w
w
23
22
21
Res.
CFEIF7
CTCIF6
w
w
7
6
5
Res.
CFEIF5
CTCIF4
w
w
RM0402 Rev 6
20
19
18
CHTIF2 CTEIF2 CDMEIF2
w
w
w
4
3
2
CHTIF0 CTEIF0 CDMEIF0
w
w
w
20
19
18
CHTIF6
CTEIF6 CDMEIF6
w
w
w
4
3
2
CHTIF4
CTEIF4 CDMEIF4
w
w
w
17
16
Res.
CFEIF2
w
1
0
Res.
CFEIF0
w
17
16
Res.
CFEIF6
w
1
0
Res.
CFEIF4
w
219/1163
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