Dfsdm Dma Transfer; Dfsdm Channel Y Registers (Y=0; Dfsdm Channel Y Configuration Register (Dfsdm_Chycfgr1) - ST STM32F412 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
Interrupt event
Regular data overrun
Analog watchdog
short-circuit detector
Channel clock absence
14.6

DFSDM DMA transfer

To decrease the CPU intervention, conversions can be transferred into memory using a
DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1
in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting
bit RDMAEN=1 in DFSDM_FLTxCR1 register.
Note: With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or
regular conversion (JEOCF or REOCF bit in DFSDM_FLTxISR register) because DMA is
reading DFSDM_FLTxJDATAR or DFSDM_FLTxRDATAR register.
14.7

DFSDM channel y registers (y=0..3)

Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register. Write access to DFSDM_CHyDATINR register can be either word access (32-bit)
or half-word access (16-bit).
14.7.1

DFSDM channel y configuration register (DFSDM_CHyCFGR1)

This register specifies the parameters used by channel y.
Address offset: 0x00 + 0x20 * y, (y = 0 to 3)
Reset value: 0x0000 0000
31 30 29
DFSDM CKOUT
Res. Res.
EN SRC
rw rw
15 14 13
DATPACK[1:0] DATMPX[1:0]
rw rw rw
376/1163
Table 90. DFSDM interrupt requests (continued)
Event flag
ROVRF
AWDF,
AWHTF[3:0],
AWLTF[3:0]
SCDF[3:0]
CKABF[3:0]
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
rw
Event/Interrupt clearing
writing CLRROVRF = 1
writing CLRAWHTF[3:0] = 1
writing CLRAWLTF[3:0] = 1
writing CLRSCDF[3:0] = 1
writing CLRCKABF[3:0] = 1
24 23 22
Res.
rw rw
8 7 6
CHIN CKAB
CHEN SCDEN
SEL EN
rw rw rw
RM0402 Rev 6
Interrupt enable
method
ROVRIE
AWDIE,
(AWDCH[3:0])
SCDIE,
(SCDEN)
CKABIE,
(CKABEN)
21 20 19 18
CKOUTDIV[7:0]
rw rw rw rw
5 4 3 2
Res. SPICKSEL[1:0]
rw rw rw
RM0402
control bit
17 16
rw rw
1 0
SITP[1:0]
rw rw