Standard Multi-Slave Communication; Figure 274. Master And Three Independent Slaves - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

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Serial peripheral interface/ inter-IC sound (SPI/I2S)

Standard multi-slave communication

In a configuration with two or more independent slaves, the master uses GPIO pins to

manage the chip select lines for each slave (see

of the slaves individually by pulling low the GPIO connected to the slave NSS input. When

this is done, a standard master and dedicated slave communication is established.

Rx shift register

Tx shift register

1. NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to

prevent any MODF error.

2. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their

MISO pin set as alternate function open-drain (see

Section 7.3.7: I/O alternate function input/output on

RM0402 Rev 6

274.). The master must select one

Tx shift register

Rx shift register

Tx shift register

Rx shift register

Tx shift register

Rx shift register

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