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Real-time clock (RTC)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 WDU[1:0]: Week day units
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format
Note:
The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
22.6.15
RTC timestamp sub second register (RTC_TSSSR)
Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
r
r
r
15
14
13
r
r
r
Bits 31:16 Reserved
Bits 15:0 SS: Sub second value
SS[15:0] is the value of the synchronous prescaler's counter when the timestamp event
occurred.
Note:
The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
22.6.16
RTC calibration register (RTC_CALR)
Address offset: 0x3C
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
r
r
r
15
14
13
CALP
CALW8 CALW16
rw
rw
rw
648/1163
28
27
26
25
Res.
Res.
Res.
r
r
r
r
12
11
10
9
r
r
r
r
28
27
26
25
Res.
Res.
Res.
Res.
r
r
r
r
12
11
10
9
Res.
Res.
Res.
Res.
r
r
r
r
24
23
22
Res.
Res.
Res.
r
r
r
8
7
6
SS[15:0]
r
r
r
24
23
22
Res.
Res.
Res.
r
r
r
8
7
6
rw
rw
rw
RM0402 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
r
r
r
r
5
4
3
2
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
r
r
r
r
5
4
3
2
CALM[8:0]
rw
rw
rw
rw
RM0402
17
16
Res.
Res.
r
r
1
0
r
r
17
16
Res.
Res.
r
r
1
0
rw
rw
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