Secure digital input/output interface (SDIO)
Bit 2 CTIMEOUTC: CTIMEOUT flag clear bit
Set by software to clear the CTIMEOUT flag.
0: CTIMEOUT not cleared
1: CTIMEOUT cleared
Bit 1 DCRCFAILC: DCRCFAIL flag clear bit
Set by software to clear the DCRCFAIL flag.
0: DCRCFAIL not cleared
1: DCRCFAIL cleared
Bit 0 CCRCFAILC: CCRCFAIL flag clear bit
Set by software to clear the CCRCFAIL flag.
0: CCRCFAIL not cleared
1: CCRCFAIL cleared
27.8.13
SDIO mask register (SDIO_MASK)
Address offset: 0x3C
Reset value: 0x0000 0000
The interrupt mask register determines which status flags generate an interrupt request by
setting the corresponding bit to 1b.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
RX
TX
RX
FIFO
FIFO
ACTIE
ACTIE
HFIE
HEIE
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable
Bit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable
Bit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable
916/1163
28
27
26
25
Res.
Res.
Res.
12
11
10
9
TX
CMD
DBCK
Res.
ACTIE
ENDIE
rw
rw
rw
Set and cleared by software to enable/disable the interrupt generated when receiving the
SDIO mode interrupt.
0: SDIO Mode Interrupt Received interrupt disabled
1: SDIO Mode Interrupt Received interrupt enabled
Set and cleared by software to enable/disable the interrupt generated by the presence of
data available in Rx FIFO.
0: Data available in Rx FIFO interrupt disabled
1: Data available in Rx FIFO interrupt enabled
Set and cleared by software to enable/disable the interrupt generated by the presence of
data available in Tx FIFO.
0: Data available in Tx FIFO interrupt disabled
1: Data available in Tx FIFO interrupt enabled
24
23
22
21
SDIO
RXD
Res.
Res.
ITIE
AVLIE
rw
rw
8
7
6
CMD
CMD
RX
DATA
SENT
REND
OVERR
ENDIE
IE
IE
IE
rw
rw
rw
rw
RM0402 Rev 6
20
19
18
RX
TX
TXD
FIFO
FIFO
AVLIE
EIE
EIE
rw
rw
rw
5
4
3
2
TX
DTIME
CTIME
UNDERR
OUTIE
OUTIE
IE
rw
rw
rw
RM0402
17
16
RX
TX
FIFO
FIFO
FIE
FIE
rw
rw
1
0
DCRC
CCRC
FAILIE
FAILIE
rw
rw
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