ST STM32F412 Reference Manual page 368

Digital filter for sigma delta modulators (DFSDM)
Analog watchdog conversions on input channels are independent from standard
conversions. In this case, the analog watchdog uses its own filters and signal processing on
each input channel independently from the main injected or regular conversions. Analog
watchdog conversions are performed in a continuous mode on the selected input channels
in order to watch channels also when main injected or regular conversions are paused
(RCIP = 0, JCIP = 0).
There are high and low threshold registers which are compared with given data values (set
by AWHT[23:0] bits in DFSDM_FLTxAWHTR register and by AWLT[23:0] bits in
DFSDM_FLTxAWLTR register).
There are 2 options for comparing the threshold registers with the data values
• Option1: in this case, the input data are taken from final output data register
(AWFSEL=0). This option is characterized by:
–
–
–
–
–
• Option2: in this case, the input data are taken from any serial data receivers output
(AWFSEL=1). This option is characterized by:
–
–
–
–
In case of input channels monitoring (AWFSEL=1), the data for comparison to threshold is
taken from channels selected by AWDCH[3:0] field (DFSDM_FLTxCR2 register). Each of
the selected channels filter result is compared to one threshold value pair (AWHT[23:0] /
AWLT[23:0]). In this case, only higher 16 bits (AWHT[23:8] / AWLT[23:8]) define the 16-bit
threshold compared with the analog watchdog filter output because data coming from the
analog watchdog filter is up to a 16-bit resolution. Bits AWHT[7:0] / AWLT[7:0] are not taken
into comparison in this case (AWFSEL=1).
Parameters of the analog watchdog filter configuration for each input channel are set in
DFSDM_CHyAWSCDR register (filter order AWFORD[1:0] and filter oversampling ratio
AWFOSR[4:0]).
Each input channel has its own comparator which compares the analog watchdog data
(from analog watchdog filter) with analog watchdog threshold values (AWHT/AWLT). When
several channels are selected (field AWDCH[3:0] field of DFSDM_FLTxCR2 register),
several comparison requests may be received simultaneously. In this case, the channel
request with the lowest number is managed first and then continuing to higher selected
channels. For each channel, the result can be recorded in a separate flag (fields
368/1163
high input data resolution (up to 24-bits)
slow response time - inappropriate for fast response applications like overcurrent
detection
for the comparison the final data are taken after bit shifting and offset data
correction
final data are available only after main regular or injected conversions are
performed
can be used in case of parallel input data source (DATMPX[1:0] ≠ 0 in
DFSDM_CHyCFGR1 register)
input serial data are processed by dedicated analog watchdog Sinc
filters with configurable oversampling ratio (1..32) and filter order (1..3) (see
AWFOSR[4:0] and AWFORD[1:0] bits setting in DFSDM_CHyAWSCDR register)
lower resolution (up to 16-bit)
fast response time - appropriate for applications which require a fast response like
overcurrent/overvoltage detection)
data are available in continuous mode independently from main regular or injected
conversions activity
RM0402 Rev 6
RM0402
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channel