Smbus Initialization - ST STM32F412 Reference Manual

RM0402
Bus idle detection
A master can assume that the bus is free if it detects that the clock and data signals have
been high for t
setup and hold
This timing parameter covers the condition where a master has been dynamically added to
the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.
SMBus
23.4.12
This section is relevant only when SMBus feature is supported. Refer to
FMPI2C
In addition to FMPI2C initialization, some other specific initialization must be done in order
to perform SMBus communication:
Received command and data acknowledge control (Slave mode)
A SMBus receiver must be able to NACK each received command or data. In order to allow
ACK control in slave mode, the Slave byte control mode must be enabled by setting the
SBC bit in the FMPI2C_CR1 register. Refer to
more details.
Specific address (Slave mode)
The specific SMBus addresses must be enabled if needed. Refer to
page 693
• The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN
bit in the FMPI2C_CR1 register.
•
The SMBus host address (0b0001 000) is enabled by setting the SMBHEN bit in the
FMPI2C_CR1 register.
•
The alert response address (0b0001100) is enabled by setting the ALERTEN bit in the
FMPI2C_CR1 register.
Packet error checking
PEC calculation is enabled by setting the PECEN bit in the FMPI2C_CR1 register. Then the
PEC transfer is managed with the help of a hardware byte counter: NBYTES[7:0] in the
FMPI2C_CR2 register. The PECEN bit must be configured before enabling the FMPI2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set
when interfacing the SMBus in slave mode. The PEC is transferred after NBYTES-1 data
have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If
RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the FMPI2C is enabled.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
greater than t
IDLE
times)
initialization
implementation.
for more details.
. (refer to Table 119: I2C-SMBus specification data
,
HIGH MAX
Slave byte control mode on page 670
RM0402 Rev 6
Section 23.3:
for
Bus idle detection on
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