Single-Wire Half-Duplex Communication; Figure 258. Usart Data Clock Timing Diagram (M=1); Figure 259. Rx Data Setup/Hold Time - ST STM32F412 Reference Manual

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
Idle or
preceding
transmission
Clock (CPOL=0,
CPHA=0)
Clock (CPOL=0,
CPHA=1)
Clock (CPOL=1,
CPHA=0)
Clock (CPOL=1,
CPHA=1)
Data on TX
(from master)
Data on RX
(from slave)
Capture
strobe
(capture strobe on SCLK
rising edge in this example)
Data on RX (from slave)
t
SETUP=
Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter
for more details.
25.4.10

Single-wire half-duplex communication

The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
•
LINEN and CLKEN bits in the USART_CR2 register,
•
SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a single-wire half-duplex protocol where the TX and
RX lines are internally connected. The selection between half- and full-duplex
communication is made with a control bit 'HALF DUPLEX SEL' (HDSEL in USART_CR3).
790/1163

Figure 258. USART data clock timing diagram (M=1)

Start
0 1
Start LSB
0 1
LSB

Figure 259. RX data setup/hold time

SCLK
t 1/16 bit time
HOLD
RM0402 Rev 6
M bits =01 (9 data bits)
2 3 4 5
2 3 4 5
*LBCL bit controls last data pulse
Valid DATA bit
t t
SETUP HOLD
Idle or next
Stop
transmission
*
*
*
*
6 7 8
MSB Stop
6 8
7
MSB
*
MSv34710V1
MSv31161V1