Figure 352. Processing A Setup Packet - ST STM32F412 Reference Manual

RM0402
1. Program the OTG_DOEPTSIZx register.
–
2. Wait for the RXFLVL interrupt (OTG_GINTSTS) and empty the data packets from the
receive FIFO.
3. Assertion of the STUP interrupt (OTG_DOEPINTx) marks a successful completion of
the SETUP data transfer.
–
•
Handling more than three back-to-back SETUP packets
Per the USB 2.0 specification, normally, during a SETUP packet error, a host does not send
more than three back-to-back SETUP packets to the same endpoint. However, the USB 2.0
specification does not limit the number of back-to-back SETUP packets a host can send to
the same endpoint. When this condition occurs, the OTG_FS controller generates an
interrupt (B2BSTUP in OTG_DOEPINTx).
•
Setting the global OUT NAK
Internal data flow:
1. When the application sets the Global OUT NAK (SGONAK bit in OTG_DCTL), the core
stops writing data, except SETUP packets, to the receive FIFO. Irrespective of the
STUPCNT = 3
On this interrupt, the application must read the OTG_DOEPTSIZx register to
determine the number of SETUP packets received and process the last received
SETUP packet.

Figure 352. Processing a SETUP packet

Wait for STP in OTG_DOEPINTx
setup_cmd[31:0 = mem[4 – 2 * rem_supcnt]
setup_cmd[63:32] = mem[5 – 2 * rem_supcnt]
Read
setup_np_in_pkt
Data IN phase
USB on-the-go full-speed (OTG_FS)
rem_supcnt=
rd_reg(OTG_DOEPTSIZx)
Find setup cmd type
Write
ctrl_rd/wr/2 stage
2-stage
setup_np_in_pkt
Status IN phase
RM0402 Rev 6
rcv_out_pkt
Data OUT phase
MSv37035V1
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