Quadspi Flag Clear Register (Quadspi_Fcr); Quadspi Data Length Register (Quadspi_Dlr) - ST STM32F412 Reference Manual

RM0402
12.5.4

QUADSPI flag clear register (QUADSPI_FCR)

Address offset: 0x000C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 CTOF: Clear timeout flag
Bit 3 CSMF: Clear status match flag
Bit 2 Reserved, must be kept at reset value.
Bit 1 CTCF: Clear transfer complete flag
Bit 0 CTEF: Clear transfer error flag
12.5.5

QUADSPI data length register (QUADSPI_DLR)

Address offset: 0x0010
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
Writing 1 clears the TOF flag in the QUADSPI_SR register
Writing 1 clears the SMF flag in the QUADSPI_SR register
Writing 1 clears the TCF flag in the QUADSPI_SR register
Writing 1 clears the TEF flag in the QUADSPI_SR register
27 26 25 24
rw rw rw rw
11 10 9 8
rw rw rw rw
RM0402 Rev 6
23 22 21
Res. Res. Res.
7 6 5
Res. Res. Res.
23 22 21
DL[31:16]
rw rw rw
7 6 5
DL[15:0]
rw rw rw
Quad-SPI interface (QUADSPI)
20 19 18
Res. Res. Res. Res.
4 3 2
CTOF CSMF Res. CTCF
w w
20 19 18
rw rw rw
4 3 2
rw rw rw
17 16
Res.
1 0
CTEF
w w
17 16
rw rw
1 0
rw rw
309/1163
316