Summary Of The Possible Dma Configurations; Stream Configuration Procedure; Table 37. Possible Dma Configurations - ST STM32F412 Reference Manual

Direct memory access controller (DMA)
9.3.17

Summary of the possible DMA configurations

The table below summarizes the different possible DMA configurations. The forbidden
configurations are highlighted in gray in the table.
DMA transfer
Source
mode
Peripheral-to- AHB
memory peripheral port
Memory-to- AHB
peripheral memory port
Memory-to- AHB
memory peripheral port
9.3.18

Stream configuration procedure

The following sequence must be followed to configure a DMA stream x (where x is the
stream number):
1. If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register,
then read this bit in order to confirm that there is no ongoing stream operation. Writing
this bit to 0 is not immediately effective since it is actually written to 0 once all the
current transfers are finished. When the EN bit is read as 0, this means that the stream
is ready to be configured. It is therefore necessary to wait for the EN bit to be cleared
before starting any stream configuration. All the stream dedicated bits set in the status
register (DMA_LISR and DMA_HISR) from the previous data block DMA transfer must
be cleared before the stream can be re-enabled.
2. Set the peripheral port register address in the DMA_SxPAR register. The data is moved
from/ to this address to/ from the peripheral port after the peripheral event.
3. Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R
register in the case of a double-buffer mode). The data is written to or read from this
memory after the peripheral event.
4. Configure the total number of data items to be transferred in the DMA_SxNDTR
register. After each peripheral event or each beat of the burst, this value is
decremented.
5. Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register.
6. If the peripheral is intended to be the flow controller and if it supports this feature, set
the PFCTRL bit in the DMA_SxCR register.
7. Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register.
8. Configure the FIFO usage (enable or disable, threshold in transmission and reception)
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Table 37. Possible DMA configurations

Flow
Destination
controller
DMA
AHB
memory port
Peripheral Forbidden
DMA
AHB
peripheral port
Peripheral Forbidden
AHB
DMA only
memory port
RM0402 Rev 6
Circular Transfer
mode type
single
Possible
burst
single
burst
single
Possible
burst
single
burst
single
Forbidden
burst
RM0402
Direct Double-
mode buffer mode
Possible
Possible
Forbidden
Possible
Forbidden
Forbidden
Possible
Possible
Forbidden
Possible
Forbidden
Forbidden
Forbidden Forbidden